公开(公告)号：US10599793B2

公开(公告)日：2020-03-24

申请号：US16459717

申请日：2019-07-02

Applicant: ZIPALOG, INC.

Inventor： Felicia James ,  Michael Krasnicki

IPC: G06F17/50 ,  G06F13/42 ,  G06F12/0875

Abstract: A computer implemented method of passive verification of an electronic design, comprising receiving an electronic design file of said electronic design comprised at least in part of a mixed signal or analog system including a plurality of subsystems. At least one analog subsystem of the plurality of subsystems has at least two design representations within the electronic design file that are intended to be equivalent for the at least one analog subsystem being simulated. First and second input subsystem data is collected for a first and second subsystem design representation of the at least two design representations from an analog stimulus to at least one input of the first and second subsystem design representation which is analog. First and second output subsystem data is collected from at least one output of the first and second subsystem design representation of the at least two design representations caused by the analog stimulus to the at least one input of the first and second subsystem design representation. At least one parameter of said first and second input subsystem data is analyzed with respect to said first and second output subsystem data. The at least one parameter of the first subsystem design representation is compared with the at least one parameter of second subsystem design representation. The electronic design file of the electronic design is verified responsive to the determined analysis between the at least one input of the subsystem and the at least one output of the subsystem for each of the first and the second subsystem design representations.

公开(公告)号：US20190213293A1

公开(公告)日：2019-07-11

申请号：US16358361

申请日：2019-03-19

Applicant: Zipalog, Inc.

Inventor： Felicia James ,  Michael Krasnicki

IPC: G06F17/50

Abstract: A computer program product embodied on a non-transitory computer usable medium includes a sequence of instructions causing at least one processor to execute a method of identification of useful untested states of an electronic design. A computer receives a computer readable representation of said electronic design having at least in one part of said electronic design an analog portion. At least one instrumented netlist is generated based at least in part upon said representation of said electronic design. At least one specification of said electronic design is also received. At least one set of valid states are generated based on said at least one specification. The at least one instrumented netlist is simulated at a behavioral level of said representation of said electronic design at a minimum number of at least one input vector. At least one verification coverage history of said electronic design is generated based in part upon said simulation. Useful untested states are identified based at least in part upon at least one of said at least one specification, said at least one instrumented netlist, said at least one set of valid states and said at least one verification coverage history.

公开(公告)号：US20180150580A1

公开(公告)日：2018-05-31

申请号：US15871210

申请日：2018-01-15

Applicant: Zipalog, Inc.

Inventor： Felicia James ,  Michael Krasnicki

IPC: G06F17/50

CPC classification number: G06F17/5036 ,  G06F17/5045 ,  G06F17/5063

Abstract: A computer implemented system and method of computer implemented method of instrumentation of an electronic design comprising receiving by a computer a computer readable representation of said electronic design having at least in one part of said electronic design, an analog portion. At least one instrumented netlist is generated based at least in part upon said representation of said electronic design. At least one specification of said electronic design is received and at least one set of valid states is generated based on said at least one specification. An analog verification coverage is determined utilizing said at least one instrumented netlist.

公开(公告)号：US09715566B2

公开(公告)日：2017-07-25

申请号：US14707689

申请日：2015-05-08

Applicant: Zipalog, Inc.

Inventor： Felicia James ,  Michael Krasnicki ,  Xiyuan Wu

IPC: G06F17/50

CPC classification number: G06F17/5063 ,  G06F17/5022 ,  G06F17/5036 ,  G06F17/5045

Abstract: A computer implemented method of translation of verification commands of an electronic design, comprises the steps of receiving the electronic design, receiving at least one analog test harness model having at least one indirect branch contribution statement, translating the at least one indirect branch contribution statement into a plurality of direct branch contribution operators based at least in part upon the at least one analog test harness model and generating a netlist based at least in part upon the translation.