公开(公告)号：US10990552B1

公开(公告)日：2021-04-27

申请号：US15944464

申请日：2018-04-03

Applicant: Xilinx, Inc.

Inventor： Goran Hk Bilski ,  Peter McColgan ,  Juan J. Noguera Serra ,  Baris Ozgul ,  Jan Langer ,  Richard L. Walke ,  Ralph D. Wittig ,  Kornelis A. Vissers ,  Philip B. James-Roxby ,  Christopher H. Dick

IPC: G06F13/40 ,  G06F13/42

Abstract: Examples herein describe techniques for communicating between data processing engines in an array of data processing engines. In one embodiment, the array is a 2D array where each of the DPEs includes one or more cores. In addition to the cores, the data processing engines can include a memory module (with memory banks for storing data) and an interconnect which provides connectivity between the engines. To transmit processed data, a data processing engine identifies a destination processing engine in the array. Once identified, the data processing engine can transmit the processed data using a reserved point-to-point communication path in the interconnect that couples the source and destination data processing engines.

公开(公告)号：US10320918B1

公开(公告)日：2019-06-11

申请号：US14574283

申请日：2014-12-17

Applicant: Xilinx, Inc.

Inventor： Michaela Blott ,  David A. Sidler ,  Kimon Karras ,  Raymond Carley ,  Kornelis A. Vissers

IPC: G06F15/16 ,  H04L29/08 ,  H04L12/741

Abstract: In an example, an integrated circuit (IC) includes a receive circuit, a transmit circuit, and a control circuit. The receive circuit includes a receive data path and a receive control interface, the receive data path coupled to store received transmission control protocol (TCP) data for a plurality of TCP sessions in a respective plurality of receive buffers in an external memory circuit external to the IC. The transmit circuit includes a transmit data path and a transmit control interface, the transmit data path coupled to read TCP data to be transmitted for the plurality of TCP sessions from a respective plurality of transmit buffers in the external memory circuit. The control circuit is coupled to the receive control interface and the transmit control interface, the control circuit configured to maintain data structures to maintain TCP state information for the plurality of TCP sessions.

公开(公告)号：US09519486B1

公开(公告)日：2016-12-13

申请号：US13683720

申请日：2012-11-21

Applicant: Xilinx, Inc.

Inventor： Michaela Blott ,  Thomas B. English ,  Kornelis A. Vissers

IPC: G06F13/00 ,  G06F9/38 ,  G06F15/78 ,  H03K19/177

CPC classification number: G06F9/3867 ,  G06F9/3897 ,  G06F15/7867 ,  G06F15/7878 ,  H03K19/17752 ,  H03K19/17756

Abstract: A method of processing data in an integrated circuit is described. The method comprises establishing a pipeline of processing blocks, wherein each processing block has a different function; coupling a data packet having data and meta-data to an input of the pipeline of processing blocks; and processing the data of the data packet using predetermined processing blocks based upon the meta-data. A device for processing data in an integrated circuit is also described.

Abstract translation: 描述了一种在集成电路中处理数据的方法。 该方法包括建立处理块流水线，其中每个处理块具有不同的功能; 将具有数据和元数据的数据分组耦合到处理块的流水线的输入; 以及使用基于所述元数据的预定处理块来处理所述数据分组的数据。 还描述了用于处理集成电路中的数据的装置。

公开(公告)号：US20150311899A1

公开(公告)日：2015-10-29

申请号：US14260580

申请日：2014-04-24

Applicant: Xilinx, Inc.

Inventor： Kimon Karras ,  Michaela Blott ,  Kornelis A. Vissers

IPC: H03K19/177 ,  G06F17/50

CPC classification number: H03K19/17748 ,  G06F17/5054 ,  G06F17/5068 ,  H03K19/17724

Abstract: A programmable IC includes a plurality of programmable resources, a plurality of shareable logic circuits coupled to the plurality of programmable resources, and a virtualization circuit. The plurality of programmable resources includes programmable logic circuits and programmable routing resources. The virtualization circuit is configured to manage sharing of the plurality of shareable logic circuits between a plurality of user designs implemented in the plurality of programmable resources. The user designs are communicatively isolated from one another on the programmable IC.

Abstract translation: 可编程IC包括多个可编程资源，耦合到多个可编程资源的多个可共享逻辑电路和虚拟化电路。 多个可编程资源包括可编程逻辑电路和可编程路由资源。 虚拟化电路被配置为管理在多个可编程资源中实现的多个用户设计之间的多个可共享逻辑电路的共享。 用户设计在可编程IC上彼此通信隔离。