公开(公告)号：US20200035805A1

公开(公告)日：2020-01-30

申请号：US16584826

申请日：2019-09-26

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chun-Hsiung LIN ,  Chia-Hao CHANG ,  Chih-Hao WANG ,  Wai-Yi LIEN ,  Chih-Chao CHOU ,  Pei-Yu WANG

IPC: H01L29/49 ,  H01L29/78 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/66 ,  H01L21/764 ,  H01L21/28

Abstract: In a method for manufacturing a semiconductor device, a gate structure is formed over a channel layer and an isolation insulating layer. A first sidewall spacer layer is formed on a side surface of the gate structure. A sacrificial layer is formed so that an upper portion of the gate structure with the first sidewall spacer layer is exposed from the sacrificial layer and a bottom portion of the gate structure with the first sidewall spacer layer is embedded in the first sacrificial layer. A space is formed between the bottom portion of the gate structure and the sacrificial layer by removing at least part of the first sidewall spacer layer. After the first sidewall spacer layer is removed, an air gap is formed between the bottom portion of the gate structure and the sacrificial layer by forming a second sidewall spacer layer over the gate structure.

公开(公告)号：US20200027960A1

公开(公告)日：2020-01-23

申请号：US16585741

申请日：2019-09-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chun-Hsiung LIN ,  Chia-Hao CHANG ,  Chih-Hao WANG ,  Wai-Yi LIEN ,  Chih-Chao CHOU ,  Pei-Yu WANG

IPC: H01L29/49 ,  H01L21/28 ,  H01L29/66 ,  H01L21/764 ,  H01L29/78 ,  H01L21/8238 ,  H01L27/092

Abstract: In a method for manufacturing a semiconductor device, a gate structure is formed over a channel layer and an isolation insulating layer. A first sidewall spacer layer is formed on a side surface of the gate structure. A sacrificial layer is formed so that an upper portion of the gate structure with the first sidewall spacer layer is exposed from the sacrificial layer and a bottom portion of the gate structure with the first sidewall spacer layer is embedded in the first sacrificial layer. A space is formed between the bottom portion of the gate structure and the sacrificial layer by removing at least part of the first sidewall spacer layer. After the first sidewall spacer layer is removed, an air gap is formed between the bottom portion of the gate structure and the sacrificial layer by forming a second sidewall spacer layer over the gate structure.

公开(公告)号：US20190267465A1

公开(公告)日：2019-08-29

申请号：US15907214

申请日：2018-02-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yi-Lun CHEN ,  Bau-Ming WANG ,  Chun-Hsiung LIN

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/02 ,  H01L21/306

Abstract: A method includes forming a semiconductor fin over a substrate; forming a helmet stack on a top surface of the semiconductor fin; forming a spacer layer over the helmet stack and on opposite sidewalls of the semiconductor fin; and etching the helmet layer and the spacer layer to expose the top surface and the sidewalls of the semiconductor fin.

公开(公告)号：US20170356953A1

公开(公告)日：2017-12-14

申请号：US15182577

申请日：2016-06-14

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chen-Han WANG ,  Chun-Hsiung LIN

IPC: G01R31/265 ,  G01R31/26 ,  H01L21/66

CPC classification number: G01R31/2653 ,  G01R31/307 ,  H01L22/14 ,  H01L22/30 ,  H01L22/34

Abstract: A method for estimating at least one electrical property of a semiconductor device is provided. The method includes forming the semiconductor device and at least one testing unit on a substrate, irradiating the testing unit with at least one electron beam, estimating electrons from the testing unit induced by the electron beam, and estimating the electrical property of the semiconductor device according to intensity of the estimated electrons from the testing unit.