公开(公告)号：US20130248980A1

公开(公告)日：2013-09-26

申请号：US13775586

申请日：2013-02-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seung-Uk HAN ,  Jae-Hoon LEE ,  Jun-Su KIM ,  Satoru YAMADA ,  Jin-Seong LEE ,  Nam-Ho JEON

IPC: H01L27/088

CPC classification number: H01L27/088 ,  H01L27/108 ,  H01L27/11

Abstract: According to an example embodiment of inventive concepts, a capacitorless memory device includes a capacitorless memory cell that includes a bit line on a substrate; a read transistor, and a write transistor. The read transistor may include first to third impurity layers stacked in a vertical direction on the bit line. The first and third layers may be a first conductive type, and the second impurity layer may be a second conductive type that differs from the first conductive type. The write transistor may include a source layer, a body layer, and a drain layer stacked in the vertical direction on the substrate, and a gate line that is adjacent to a side surface of the body layer. The gate line may be spaced apart from the side surface of the body layer. The source layer may be adjacent to a side surface of the second impurity layer.

Abstract translation: 根据本发明构思的示例性实施例，一种无电容器存储器件包括：无电容器存储器单元，其在衬底上包括位线; 读取晶体管和写入晶体管。 读取晶体管可以包括在位线上沿垂直方向堆叠的第一至第三杂质层。 第一和第三层可以是第一导电类型，并且第二杂质层可以是不同于第一导电类型的第二导电类型。 写入晶体管可以包括在基板上沿垂直方向堆叠的源极层，主体层和漏极层，以及与主体层的侧表面相邻的栅极线。 栅极线可以与主体层的侧表面间隔开。 源极层可以与第二杂质层的侧表面相邻。