Semiconductor devices
    21.
    发明授权

    公开(公告)号:US11758713B2

    公开(公告)日:2023-09-12

    申请号:US17386008

    申请日:2021-07-27

    CPC classification number: H10B12/50 H01L27/092 H10B12/315

    Abstract: A semiconductor device includes first and second trenches in respective first and second regions in a substrate, a first isolation structure having a first inner wall oxide pattern, a first liner, and a first filling insulation pattern sequentially stacked I the first trench, a second isolation structure having a second inner wall oxide pattern, a second liner, and a second filling insulation pattern sequentially stacked I the second trench, a first gate structure having a first high-k dielectric pattern, a first P-type metal pattern, and a first N-type metal pattern sequentially stacked on the first region, and a second gate structure having a second high-k dielectric pattern and a second N-type metal pattern sequentially stacked on the second region, wherein the first and second liners protrude above upper surfaces of the first and second inner wall oxide patterns and the first and second filling insulation patterns, respectively.

    SEMICONDUCTOR CHIP AND SEMICONDUCTOR PACKAGE INCLUDING THE SAME

    公开(公告)号:US20210134745A1

    公开(公告)日:2021-05-06

    申请号:US16922828

    申请日:2020-07-07

    Abstract: Disclosed embodiments include a semiconductor chip including a semiconductor substrate having a top surface with a top connection pad disposed therein, and a protection insulation layer comprising an opening therein, the protection insulation layer not covering at least a portion of the top connection pad, on the semiconductor substrate. The protection insulation layer may include: a bottom protection insulation layer, a cover insulation layer comprising a side cover part that covers at least a portion of a side surface of the bottom protection insulation layer and a top cover part disposed apart from the side cover part to cover at least a portion of a top surface of the bottom protection insulation layer. The protection insulation layer may further include a top protection insulation layer on the top cover part.

    SEMICONDUCTOR CHIP INCLUDING LOW-K DIELECTRIC LAYER

    公开(公告)号:US20210057328A1

    公开(公告)日:2021-02-25

    申请号:US16848246

    申请日:2020-04-14

    Abstract: A semiconductor chip includes a device layer on a substrate, the device layer including a plurality of semiconductor devices; a wiring structure and a lower inter-wiring dielectric layer each on the device layer, the lower inter-wiring dielectric layer surrounding the wiring structure and having a lower permittivity than silicon oxide; an upper inter-wiring dielectric layer arranged on the lower inter-wiring dielectric layer; an isolation recess arranged along an edge of the substrate, the isolation recess formed on side surfaces of the lower and upper inter-wiring dielectric layers and having a bottom surface at a level equal to or lower than that of a bottom surface of the lower inter-wiring dielectric layer; and a cover dielectric layer covering the side surfaces of the lower and upper inter-wiring dielectric layers and the bottom surface of the isolation recess.

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