公开(公告)号：US11581257B2

公开(公告)日：2023-02-14

申请号：US17338815

申请日：2021-06-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyuek Jae Lee ,  Ji Hoon Kim ,  Tae Hun Kim ,  Ji Seok Hong ,  Ji Hwan Hwang

IPC: H01L23/528 ,  H01L23/31 ,  H01L23/367 ,  H01L23/498 ,  H01L23/00 ,  H01L25/065 ,  H01L21/78

Abstract: A semiconductor package is provided. The semiconductor package includes a lower structure including an upper insulating layer and an upper pad; and a semiconductor chip provided on the lower structure and comprising a lower insulating layer and a lower pad. The lower insulating layer is in contact with and coupled to the upper insulating layer and the lower pad is in contact with and coupled to the upper pad, and a lateral side of the semiconductor chip extends between an upper side and a lower side of the semiconductor chip and comprises a recessed portion.

公开(公告)号：US11145626B2

公开(公告)日：2021-10-12

申请号：US16589541

申请日：2019-10-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ji Hwan Hwang ,  Ji Hoon Kim ,  Ji Seok Hong ,  Tae Hun Kim ,  Hyuek Jae Lee

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/48 ,  H01L21/768 ,  H01L25/00

Abstract: A semiconductor package includes a base structure having a base pad, a first semiconductor chip on the base structure, and having a first connection pad bonded to the base pad, a first bonding structure including an base insulation layer of a base structure and a first lower insulation layer of the first semiconductor chip bonded to the base insulation layer, a second semiconductor chip on the first semiconductor chip, and having a second connection pad connected to the first through-electrode, and a second bonding structure including a first upper insulation layer of the first semiconductor chip, and a second lower insulation layer of the second semiconductor chip bonded to the first upper insulation layer, and the first upper insulation layer has a dummy insulation portion extending onto the base structure around the first semiconductor chip.

公开(公告)号：US10679933B2

公开(公告)日：2020-06-09

申请号：US16598046

申请日：2019-10-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sun Ho Kim ,  Ji Hoon Kim ,  Ha Young Ahn ,  Shang Hoon Seo ,  Seung Yeop Kook ,  Sung Won Jeong

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/538 ,  H01L23/31 ,  H01L23/13

Abstract: A fan-out semiconductor package includes: an interconnection member including a first insulating layer, first and second pads respectively disposed on opposite sides of the first insulating layer and a first via connecting the first and second pads to each other; a semiconductor chip disposed on the interconnection member; and an encapsulant encapsulating at least portions of the semiconductor chip. A center line of the first via is out of alignment with at least one of a center line of the first pad and a center line of the second pad.

公开(公告)号：US10461008B2

公开(公告)日：2019-10-29

申请号：US15205483

申请日：2016-07-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sung Won Jeong ,  Ji Hoon Kim ,  Sun Ho Kim ,  Shang Hoon Seo ,  Seung Yeop Kook ,  Christian Romero

IPC: H01L23/31 ,  H01L23/48 ,  H01L25/10 ,  H01L23/00 ,  H01L23/29 ,  H01L23/552

Abstract: An electronic component package includes a wiring part including an insulating layer, a conductive pattern formed on the insulating layer, and a conductive via connected to the conductive pattern through the insulating layer, an electronic component disposed on the wiring part, a frame disposed on the wiring part and having a component disposition region defined by an inner wall of the frame surrounding the electronic component, and an encapsulant filling at least a portion of the component disposition region. A portion of the inner wall of the frame forms a protrusion protruding toward the electronic component.

公开(公告)号：USD787554S1

公开(公告)日：2017-05-23

申请号：US29524767

申请日：2015-04-23

Applicant: Samsung Electronics Co., Ltd.

Designer： Ji Hoon Kim ,  Ji Hye Kim ,  Jong Hyun Shin

公开(公告)号：USD748646S1

公开(公告)日：2016-02-02

申请号：US29482353

申请日：2014-02-18

Applicant: Samsung Electronics Co., Ltd.

Designer： Ji Hoon Kim ,  Jong Hyun Shin

公开(公告)号：US20150279590A1

公开(公告)日：2015-10-01

申请号：US14671150

申请日：2015-03-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Cheol Hee KIM ,  Ji Hoon Kim

IPC: H01H13/14

CPC classification number: H01H13/14 ,  H01H2215/006

Abstract: An electronic device is provided. The electronic device includes a housing; an input button inserted into a button hole formed at the housing and disposed to allow a state change, a dome switch having a dome part and disposed to be spaced apart from the input button, a flexible member interposed between the input button and the dome switch and disposed to be pressed in a direction of the dome part by a state change of the input button, and a rigid member interposed between the dome part and the flexible member to deliver the state change of the input button delivered through the flexible member to the dome part.

Abstract translation: 提供电子设备。 电子设备包括壳体; 插入到形成在壳体上并设置成允许状态改变的按钮孔中的输入按钮，具有圆顶部并且设置成与输入按钮间隔开的圆顶开关，插入在输入按钮和圆顶开关之间的柔性构件 并且通过输入按钮的状态改变而设置成沿着圆顶部分的方向被按压，以及插入在圆顶部分和柔性构件之间的刚性构件，以将通过柔性构件传送的输入按钮的状态改变传递到 圆顶部分。

公开(公告)号：US20230268266A1

公开(公告)日：2023-08-24

申请号：US18186618

申请日：2023-03-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sun Ho Kim ,  Ji Hoon Kim ,  Ha Young Ahn ,  Shang Hoon Seo ,  Seung Yeop Kook ,  Sung Won Jeong

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/538 ,  H01L23/31

CPC classification number: H01L23/49838 ,  H01L23/3128 ,  H01L23/5389 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/05 ,  H01L24/19 ,  H01L24/20 ,  H01L23/13 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2924/3512 ,  H01L2924/18162

Abstract: A fan-out semiconductor package includes: an interconnection member including a first insulating layer, first and second pads respectively disposed on opposite sides of the first insulating layer, and a first via connecting the first and second pads to each other; a semiconductor chip disposed on the interconnection member; and an encapsulant encapsulating at least portions of the semiconductor chip. At least a portion of a first wall of a first trench of the first insulating layer and at least a portion of a second wall of a second trench of the second insulating layer overlap each other vertically. At least a portion of the second wall of the second trench and at least a portion of a third wall of a third trench of the third insulating layer overlap each other vertically

公开(公告)号：US11056432B2

公开(公告)日：2021-07-06

申请号：US16451944

申请日：2019-06-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyuek Jae Lee ,  Ji Hoon Kim ,  Tae Hun Kim ,  Ji Seok Hong ,  Ji Hwan Hwang

IPC: H01L23/528 ,  H01L23/00 ,  H01L23/498 ,  H01L23/367 ,  H01L23/31 ,  H01L25/065

Abstract: A semiconductor package is provided. The semiconductor package includes a lower structure including an upper insulating layer and an upper pad; and a semiconductor chip provided on the lower structure and comprising a lower insulating layer and a lower pad. The lower insulating layer is in contact with and coupled to the upper insulating layer and the lower pad is in contact with and coupled to the upper pad, and a lateral side of the semiconductor chip extends between an upper side and a lower side of the semiconductor chip and comprises a recessed portion.

公开(公告)号：US10861784B2

公开(公告)日：2020-12-08

申请号：US16884316

申请日：2020-05-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sun Ho Kim ,  Ji Hoon Kim ,  Ha Young Ahn ,  Shang Hoon Seo ,  Seung Yeop Kook ,  Sung Won Jeong

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/538 ,  H01L23/31 ,  H01L23/13

Abstract: A fan-out semiconductor package includes: an interconnection member including a first insulating layer, first and second pads respectively disposed on opposite sides of the first insulating layer and a first via connecting the first and second pads to each other; a semiconductor chip disposed on the interconnection member; and an encapsulant encapsulating at least portions of the semiconductor chip. A center line of the first via is out of alignment with at least one of a center line of the first pad and a center line of the second pad.