公开(公告)号：US10733760B2

公开(公告)日：2020-08-04

申请号：US16597846

申请日：2019-10-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Zhengping Ji ,  Lilong Shi ,  Yibing Michelle Wang ,  Hyun Surk Ryu ,  Ilia Ovsiannikov

IPC: G06K9/00 ,  G06T7/73

Abstract: A Dynamic Vision Sensor (DVS) pose-estimation system includes a DVS, a transformation estimator, an inertial measurement unit (IMU) and a camera-pose estimator based on sensor fusion. The DVS detects DVS events and shapes frames based on a number of accumulated DVS events. The transformation estimator estimates a 3D transformation of the DVS camera based on an estimated depth and matches confidence-level values within a camera-projection model such that at least one of a plurality of DVS events detected during a first frame corresponds to a DVS event detected during a second subsequent frame. The IMU detects inertial movements of the DVS with respect to world coordinates between the first and second frames. The camera-pose estimator combines information from a change in a pose of the camera-projection model between the first frame and the second frame based on the estimated transformation and the detected inertial movements of the DVS.

公开(公告)号：US20200026978A1

公开(公告)日：2020-01-23

申请号：US16552619

申请日：2019-08-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ilia Ovsiannikov ,  Ali Shafiee Ardestani ,  Joseph H. Hassoun ,  Lei Wang ,  Sehwan Lee ,  JoonHo Song ,  Jun-Woo Jang ,  Yibing Michelle Wang ,  Yuecheng Li

IPC: G06N3/04 ,  G06F17/16 ,  G06N3/08

Abstract: A neural processor. In some embodiments, the processor includes a first tile, a second tile, a memory, and a bus. The bus may be connected to the memory, the first tile, and the second tile. The first tile may include: a first weight register, a second weight register, an activations buffer, a first multiplier, and a second multiplier. The activations buffer may be configured to include: a first queue connected to the first multiplier and a second queue connected to the second multiplier. The first queue may include a first register and a second register adjacent to the first register, the first register being an output register of the first queue. The first tile may be configured: in a first state: to multiply, in the first multiplier, a first weight by an activation from the output register of the first queue, and in a second state: to multiply, in the first multiplier, the first weight by an activation from the second register of the first queue.

公开(公告)号：US10447958B2

公开(公告)日：2019-10-15

申请号：US16149023

申请日：2018-10-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yibing Michelle Wang ,  Ilia Ovsiannikov

IPC: H04N5/00 ,  H04N5/378 ,  H04N5/374 ,  H04N5/376 ,  H04N17/00 ,  H04N5/232

Abstract: Using the same image sensor to capture a two-dimensional (2D) image and three-dimensional (3D) depth measurements for a 3D object. A laser point-scans the surface of the object with light spots, which are detected by a pixel array in the image sensor to generate the 3D depth profile of the object using triangulation. Each row of pixels in the pixel array forms an epipolar line of the corresponding laser scan line. Timestamping provides a correspondence between the pixel location of a captured light spot and the respective scan angle of the laser to remove any ambiguity in triangulation. An Analog-to-Digital Converter (ADC) in the image sensor operates as a Time-to-Digital (TDC) converter to generate timestamps. A timestamp calibration circuit is provided on-board to record the propagation delay of each column of pixels in the pixel array and to provide necessary corrections to the timestamp values generated during 3D depth measurements.

公开(公告)号：US12182577B2

公开(公告)日：2024-12-31

申请号：US16847504

申请日：2020-04-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ilia Ovsiannikov ,  Ali Shafiee Ardestani ,  Hamzah Ahmed Ali Abdelaziz ,  Joseph H. Hassoun

IPC: G06F9/38 ,  G06F15/80

Abstract: A processor. In some embodiments, the processor includes: a first tile, the first tile being configured: to feed a first nibble from a third queue, through a first shuffler, to a first multiplier, and to multiply, in the first multiplier, the first nibble from the third queue by a first nibble of a third weight; to feed a second nibble from the third queue, through the first shuffler, to a second multiplier, and to multiply, in the second multiplier, the second nibble from the third queue by a second nibble of the third weight; and to feed a first nibble from a fourth queue, through the first shuffler, to a third multiplier, and to multiply, in the third multiplier, the first nibble from the fourth queue by a first nibble of a fourth weight.

公开(公告)号：US12099912B2

公开(公告)日：2024-09-24

申请号：US16446610

申请日：2019-06-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ilia Ovsiannikov ,  Ali Shafiee Ardestani ,  Joseph H. Hassoun ,  Lei Wang ,  Sehwan Lee ,  JoonHo Song ,  Jun-Woo Jang ,  Yibing Michelle Wang ,  Yuecheng Li

IPC: G06N3/04 ,  G06F9/30 ,  G06F17/15 ,  G06F17/16 ,  G06N3/08 ,  G06T9/00

CPC classification number: G06N3/04 ,  G06F17/153 ,  G06F17/16 ,  G06N3/08 ,  G06T9/002 ,  G06F9/3001

Abstract: A neural processor. In some embodiments, the processor includes a first tile, a second tile, a memory, and a bus. The bus may be connected to the memory, the first tile, and the second tile. The first tile may include: a first weight register, a second weight register, an activations buffer, a first multiplier, and a second multiplier. The activations buffer may be configured to include: a first queue connected to the first multiplier and a second queue connected to the second multiplier. The first queue may include a first register and a second register adjacent to the first register, the first register being an output register of the first queue. The first tile may be configured: in a first state: to multiply, in the first multiplier, a first weight by an activation from the output register of the first queue, and in a second state: to multiply, in the first multiplier, the first weight by an activation from the second register of the first queue.

公开(公告)号：US12073302B2

公开(公告)日：2024-08-27

申请号：US18219904

申请日：2023-07-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ilia Ovsiannikov ,  Ali Shafiee Ardestani ,  Joseph H. Hassoun ,  Lei Wang ,  Sehwan Lee ,  JoonHo Song ,  Jun-Woo Jang ,  Yibing Michelle Wang ,  Yuecheng Li

IPC: G06N3/04 ,  G06F9/30 ,  G06F17/15 ,  G06F17/16 ,  G06N3/08 ,  G06T9/00

CPC classification number: G06N3/04 ,  G06F17/153 ,  G06F17/16 ,  G06N3/08 ,  G06T9/002 ,  G06F9/3001

Abstract: A neural processor. In some embodiments, the processor includes a first tile, a second tile, a memory, and a bus. The bus may be connected to the memory, the first tile, and the second tile. The first tile may include: a first weight register, a second weight register, an activations buffer, a first multiplier, and a second multiplier. The activations buffer may be configured to include: a first queue connected to the first multiplier and a second queue connected to the second multiplier. The first queue may include a first register and a second register adjacent to the first register, the first register being an output register of the first queue. The first tile may be configured: in a first state: to multiply, in the first multiplier, a first weight by an activation from the output register of the first queue, and in a second state: to multiply, in the first multiplier, the first weight by an activation from the second register of the first queue.

公开(公告)号：US12015429B2

公开(公告)日：2024-06-18

申请号：US17969671

申请日：2022-10-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ilia Ovsiannikov ,  Ali Shafiee Ardestani ,  Lei Wang ,  Joseph H. Hassoun

IPC: H03M7/30 ,  G06F9/30 ,  G06F9/38 ,  H03M7/40 ,  H04L5/02

CPC classification number: H03M7/3066 ,  G06F9/30018 ,  G06F9/30036 ,  G06F9/30145 ,  G06F9/3818 ,  G06F9/3851 ,  H03M7/40 ,  H03M7/6005 ,  H03M7/6011 ,  H03M7/6023 ,  H04L5/023

Abstract: A multichannel data packer includes a plurality of two-input multiplexers and a controller. The plurality of two-input multiplexers is arranged in 2N rows and N columns in which N is an integer greater than 1. Each input of a multiplexer in a first column receives a respective bit stream of 2N channels of bit streams. Each respective bit stream includes a bit-stream length based on data in the bit stream. The multiplexers in a last column output 2N channels of packed bit streams each having a same bit-stream length. The controller controls the plurality of multiplexers so that the multiplexers in the last column output the 2N channels of bit streams that each has the same bit-stream length.

公开(公告)号：US12008474B2

公开(公告)日：2024-06-11

申请号：US17016363

申请日：2020-09-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Zhengping Ji ,  John Wakefield Brothers ,  Ilia Ovsiannikov ,  Eunsoo Shim

IPC: G06N20/10 ,  G06N3/08 ,  G06N3/082 ,  G06N20/20

CPC classification number: G06N3/082

Abstract: An embodiment includes a method, comprising: pruning a layer of a neural network having multiple layers using a threshold; and repeating the pruning of the layer of the neural network using a different threshold until a pruning error of the pruned layer reaches a pruning error allowance.

公开(公告)号：US11875268B2

公开(公告)日：2024-01-16

申请号：US18148422

申请日：2022-12-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Zhengping Ji ,  Ilia Ovsiannikov ,  Yibing Michelle Wang ,  Lilong Shi

IPC: G06N3/084 ,  G06F18/213 ,  G06N3/045 ,  G06V30/18 ,  G06F18/24 ,  G06F18/2413 ,  G06V30/19 ,  G06V10/77 ,  G06V10/82 ,  G06V10/44 ,  G06V30/10

CPC classification number: G06N3/084 ,  G06F18/213 ,  G06F18/24 ,  G06F18/24137 ,  G06N3/045 ,  G06V10/454 ,  G06V10/7715 ,  G06V10/82 ,  G06V30/18057 ,  G06V30/19127 ,  G06V30/19173 ,  G06V30/10

Abstract: A client device configured with a neural network includes a processor, a memory, a user interface, a communications interface, a power supply and an input device, wherein the memory includes a trained neural network received from a server system that has trained and configured the neural network for the client device. A server system and a method of training a neural network are disclosed.

公开(公告)号：US11621724B2

公开(公告)日：2023-04-04

申请号：US16847642

申请日：2020-04-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ilia Ovsiannikov ,  Lei Wang

IPC: H04L5/02 ,  G06F9/30 ,  H03M7/30 ,  H03M7/40 ,  G06F9/38

Abstract: A data-sparsity homogenizer includes a plurality of multiplexers and a controller. The plurality of multiplexers receives 2N bit streams of non-homogenous sparse data in which the non-homogenous sparse data includes non-zero value data clumped together. The plurality of multiplexers is arranged in 2N rows and N columns. Each input of a multiplexer in a first column receives a respective bit stream of the 2N bit streams of non-homogenized sparse data, and the multiplexers in a last column output 2N bit streams of sparse data that is more homogenous than the non-homogenous sparse data of the 2N bit streams. The controller controls the plurality of multiplexers so that the multiplexers in the last column output the 2N channels of bit streams of sparse data that is more homogeneous than the non-homogenous sparse data of the 2N bit streams.