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公开(公告)号：US20240264605A1
公开(公告)日：2024-08-08
申请号：US18639611
申请日：2024-04-18
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Hankyeol KIM , Seungbeom HAN , Kyongsu KIM , Dongmin SHIN , Sangwuk CHAE , Heewon CHAE , Junu HONG
CPC classification number: G05D1/2295 , G05D1/243
Abstract: A robot includes: a light and detection ranging (“Lidar”) sensor; a driving module; a memory configured to store first map data corresponding to a first traveling space; and at least one processor configured to: acquire sensing data through the Lidar sensor at a traveling start position of the robot, control the driving module to move the robot in a state in which a position corresponding to the traveling start position of the robot is not identified on the first map data based on the acquired sensing data, acquire second map data based on the sensing data acquired through the Lidar sensor while the robot is moving, identify whether a second traveling space corresponding to the second map data matches the first traveling space based on probability information included in the first map data and position information on one or more objects included in the second map data, and identify the traveling start position of the robot on the first map data based on the traveling start position of the robot on the second map data and the position information on the one or more objects in a state in which it is identified that the second traveling space matches the first traveling space.
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公开(公告)号：US20240214007A1
公开(公告)日：2024-06-27
申请号：US18601237
申请日：2024-03-11
Applicant: Samsung Electronics Co., Ltd.
Inventor： Yoondo LEE , Sigwan KIM , Hyelee SONG , Dongryul SHIN , Dongmin SHIN , Yoonjae LEE , Handug LEE , Woosik CHO , Weonjai CHOI , Taewook HAM , Kyunggu KIM , Hongpyo BAE , Jinwoo JUNG , Youngjun CHO
CPC classification number: H04B1/0064 , H01Q1/243 , H01Q5/50 , H01Q21/08 , H05K1/0243 , H05K1/0277 , H05K7/1427 , H05K2201/10098
Abstract: In embodiments, an electronic device may include a housing having an inner space, a printed circuit board (PCB) disposed in the inner space of the housing, a first antenna structure disposed at a position spaced apart from the PCB, and transmitting and/or receiving a radio signal in a first frequency band, at least one second antenna structure disposed at a position spaced apart from the PCB, and transmitting and/or receiving a radio signal in a second frequency band different from the first frequency band, and a flexible substrate electrically connecting the PCB and the first antenna structure. The flexible substrate may include a first connecting portion electrically connected to the PCB, an interconnecting portion extended from the first connecting portion to the first antenna structure, at least one branch portion branched from at least a part of the interconnecting portion, and extended to the at least one second antenna structure, at least one first conductive path disposed in the interconnecting portion, and electrically connecting the first connecting portion and the first antenna structure, and at least one second conductive path disposed in the interconnecting portion and the at least one branch portion, and electrically connecting the first connecting portion and the at least one second antenna structure.
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Patent Agency Ranking
公开(公告)号：US20230057932A1
公开(公告)日：2023-02-23
申请号：US17685024
申请日：2022-03-02
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Kwanwoo NOH , Hyeonjong SONG , Wijik LEE , Hongrak SON , Dongmin SHIN , Seonghyeog CHOI
IPC: G06F3/06
Abstract: Provided are a memory controller calculating an optimal read level, a memory system including the memory controller, and an operating method of the memory controller. The memory controller includes: a processor configured to control a memory operation on the memory device; and a read level calculation module configured to: receive N counting values corresponding to N read levels generated based on a counting operation on data read by using a plurality of read levels, model at least two cell count functions having selected read levels that are selected from the N read levels as inputs, and the N counting values corresponding to the selected read levels as outputs, and calculate an optimal read level based on an optimal cell count function selected from the at least two cell count functions, wherein N is an integer equal to or greater than four, wherein the N counting values include counting values corresponding to at least four different read levels.
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公开(公告)号：US20220254433A1
公开(公告)日：2022-08-11
申请号：US17469422
申请日：2021-09-08
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Sehwan PARK , Jinyoung KIM , Youngdeok SEO , Dongmin SHIN , Joonsuc JANG , Sungmin JOE
Abstract: A storage device includes a nonvolatile memory device and a memory controller to control the nonvolatile memory device. The nonvolatile memory device includes a memory cell array. The memory cell array includes a normal cell region, a parity cell region and a redundancy cell region. First bit-lines are connected to the normal cell region and the parity cell region and second bit-lines are connected to the redundancy cell region. The memory controller includes an error correction code (ECC) engine to generate parity data. The memory controller stores user data in the normal cell region, controls the nonvolatile memory device to perform a column repair on first defective bit-lines among the first bit-lines, assigns additional column addresses to the first defective bit-lines and the second bit-lines and stores at least a portion of the parity data in a region corresponding to the additionally assigned column addresses.
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公开(公告)号：US20220130485A1
公开(公告)日：2022-04-28
申请号：US17244195
申请日：2021-04-29
Applicant: Samsung Electronics Co., Ltd.
Inventor： Youngjun HWANG , Heeyoul KWAK , Bohwan JUN , Hongrak SON , Dongmin SHIN , Geunyeong YU
Abstract: A memory device includes a cell array including a plurality of pages and a control logic configured to control program and read operations of the cell array. The control logic controls the program and read operations to store first through N-th codewords in a first page among the pages and program a page parity corresponding in common to the first through N-th codewords to the first page in response to a program command for a page unit and to selectively read the first codeword among the first through N-th codewords in response to a read command for a sub-page unit, where N is an integer of at least 2. The first codeword includes first sub-page data and a first sub-parity corresponding thereto, and the first sub-parity includes information for correcting an error in the first sub-page data through error correction code (ECC) decoding independently performed on each codeword.
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公开(公告)号：US20210397514A1
公开(公告)日：2021-12-23
申请号：US17134961
申请日：2020-12-28
Applicant: Samsung Electronics Co., Ltd.
Inventor： Youngjun HWANG , Hongrak SON , Dongmin SHIN
Abstract: An error check code (ECC) decoder includes a buffer, a data converter and a decoding circuit. The buffer stores a plurality of read pages read from a plurality of multi-level cells connected to a same wordline. The data converter adjusts reliability parameters of read bits of the plurality of read pages based on state-bit mapping information and the plurality of read pages to generate a plurality of ECC input data respectively corresponding to the plurality of read pages. The state-bit mapping information indicate mapping relationships between states and bits stored in the plurality of multi-level cells. The decoding circuit performs an ECC decoding operation with respect to the plurality of read pages based on the plurality of ECC input data. An error correction probability is increased by adjusting the reliability parameters of read bits based on the state-bit mapping information.
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27.发明申请公开(公告)号：US20170102996A1
公开(公告)日：2017-04-13
申请号：US15288227
申请日：2016-10-07
Applicant: Samsung Electronics Co., Ltd.
Inventor： Geunyeong YU , Junjin KONG , Beom Kyu SHIN , Myungkyu LEE , Jiyoup KIM , Dongmin SHIN
CPC classification number: G06F11/1092 , G06F3/0619 , G06F3/064 , G06F3/0683
Abstract: A redundant array of inexpensive disks (RAID) controller of a RAID storage system that includes one or more storage devices includes an error correction code (ECC) result manager configured to manage information of ECC result indicators when a data chunk that includes one or more ECC data units having an uncorrectable ECC error is read from among a plurality of data chunks dispersively stored in the one or more storage devices, each of the plurality of data chunks including a plurality of ECC data units, the ECC result indicators respectively indicating whether the plurality of ECC data units included in the plurality of data chunks has an uncorrectable ECC error; and an uncorrectable error counter configured to calculate a number of ECC result indicators indicating an uncorrectable ECC error among ECC result indicators corresponding to ECC data units having a same order in each of the plurality pluralit.y of data chunks.
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