公开(公告)号：US12237324B2

公开(公告)日：2025-02-25

申请号：US18052726

申请日：2022-11-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jangeun Lee ,  Minjoo Lee ,  Eunyoung Lee ,  Minsik Kim

IPC: H10B12/00 ,  H01L21/02 ,  H01L27/06

Abstract: An integrated circuit device according may include a plurality of gate structures embedded in a substrate, a direct contact on the substrate between the plurality of gate structures, and a bit line electrode layer on the direct contact. The bit line electrode layer has a thickness of about 10 nm to 30 nm. The bit line electrode layer may include a molybdenum tungsten (MoW) alloy including molybdenum (Mo) a range of about 25 at % to about 75 at %.

公开(公告)号：US20210050383A1

公开(公告)日：2021-02-18

申请号：US16884769

申请日：2020-05-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ung Hwan Pi ,  Sung Chul Lee ,  Jangeun Lee

IPC: H01L27/22 ,  H01L43/02

Abstract: A magnetic memory device includes a first cell array structure including first and second free magnetic patterns which extend in a first direction parallel to a top surface of a substrate and are spaced apart from each other in a second direction intersecting the first direction, and a second cell array structure including a third free magnetic pattern between the first and second free magnetic patterns and a fourth free magnetic pattern spaced apart from the third free magnetic pattern with the second free magnetic pattern therebetween. The first cell array structure further includes a first transistor region including first transistors connected to the first and second free magnetic patterns. The second cell array structure further includes a second transistor region including second transistors connected to the third and fourth free magnetic patterns. The second transistor region is spaced apart from the first transistor region in the first direction.

公开(公告)号：US20160005954A1

公开(公告)日：2016-01-07

申请号：US14712792

申请日：2015-05-14

Applicant: Samsung Electronics Co., LTD.

Inventor： Dustin William Erickson ,  Xueti Tang ,  Jangeun Lee

IPC: H01L43/02 ,  H01L43/10 ,  H01L43/12 ,  H01L43/08

CPC classification number: H01L43/12 ,  H01L43/08

Abstract: A method for providing a magnetic junction usable in a magnetic device and the magnetic junction are described. The method includes providing a free layer, a pinned layer and a nonmagnetic spacer layer between the free layer and the pinned layer. The free layer is switchable between a plurality of stable magnetic states when a write current is passed through the magnetic junction. At least one of the step of providing the free layer includes a first plurality of steps and the step of providing the pinned layer includes a second plurality of steps. The first and second plurality of steps include depositing a portion of a layer, depositing a sacrificial layer, annealing the portion of the magnetic junction under the sacrificial layer, and depositing a remaining portion of the layer. The layer may be the free layer, the pinned layer, or both.

Abstract translation: 描述了一种用于提供可用于磁性装置和磁结的磁结的方法。 该方法包括在自由层和钉扎层之间提供自由层，钉扎层和非磁性间隔层。 当写入电流通过磁结时，自由层可在多个稳定磁状态之间切换。 提供自由层的步骤中的至少一个包括第一多个步骤，并且提供钉扎层的步骤包括第二多个步骤。 第一和第二多个步骤包括沉积层的一部分，沉积牺牲层，将牺牲层下面的磁结的部分退火，以及沉积该层的剩余部分。 该层可以是自由层，钉扎层或两者。