公开(公告)号：US20230378311A1

公开(公告)日：2023-11-23

申请号：US18197420

申请日：2023-05-15

Applicant: STMicroelectronics (Rousset) SAS ,  STMicroelectronics (Crolles 2) SAS

Inventor： Guillaume GUIRLEO ,  Abderrezak MARZAKI ,  Thomas CABOUT

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/308 ,  H01L21/762

CPC classification number: H01L29/66136 ,  H01L21/02381 ,  H01L21/308 ,  H01L21/0262 ,  H01L21/02293 ,  H01L21/76224

Abstract: A method of manufacturing a PN junction includes successive steps for: forming at least one trench in a semiconductor substrate of a first conductivity type; and filling the at least one trench with a semiconductor material of a second conductivity type, different from the first conductivity type.

公开(公告)号：US20230238272A1

公开(公告)日：2023-07-27

申请号：US18127751

申请日：2023-03-29

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Franck JULIEN ,  Abderrezak MARZAKI

IPC: H01L21/762 ,  H01L21/02 ,  H01L21/306 ,  H01L21/308 ,  H01L21/311 ,  H01L25/16 ,  H01L25/18

CPC classification number: H01L21/76224 ,  H01L21/0217 ,  H01L21/30625 ,  H01L21/308 ,  H01L21/31116 ,  H01L25/16 ,  H01L25/18

Abstract: Trenches of different depths in an integrated circuit are formed by a process utilizes a dry etch. A first stop layer is formed over first and second zones of the substrate. A second stop layer is formed over the first stop layer in only the second zone. A patterned mask defines the locations where the trenches are to be formed. The dry etch uses the mask to etch in the first zone, in a given time, through the first stop layer and then into the substrate down to a first depth to form a first trench. This etch also, at the same time, etch in the second zone through the second stop layer, and further through the first stop layer, and then into the substrate down to a second depth to form a second trench. The second depth is shallower than the first depth.

公开(公告)号：US20230223332A1

公开(公告)日：2023-07-13

申请号：US18118935

申请日：2023-03-08

Applicant: STMicroelectronics (Rousset) SAS ,  STMicroelectronics (Crolles 2) SAS

Inventor： Abderrezak MARZAKI ,  Arnaud REGNIER ,  Stephan NIEL

IPC: H01L23/522

CPC classification number: H01L23/5223 ,  H10B41/35 ,  H01L28/91 ,  H01L28/92

Abstract: First and second wells are formed in a semiconductor substrate. First and second trenches in the first second wells, respectively, each extend vertically and include a central conductor insulated by a first insulating layer. A second insulating layer is formed on a top surface of the semiconductor substrate. The second insulating layer is selectively thinned over the second trench. A polysilicon layer is deposited on the second insulating layer and then lithographically patterned to form: a first polysilicon portion over the first well that is electrically connected to the central conductor of the first trench to form a first capacitor plate, a second capacitor plate formed by the first well; and a second polysilicon portion over the second well forming a floating gate electrode of a floating gate transistor of a memory cell having an access transistor whose control gate is formed by the central conductor of the second trench.

公开(公告)号：US20230207449A1

公开(公告)日：2023-06-29

申请号：US18116672

申请日：2023-03-02

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Abderrezak MARZAKI

IPC: H01L23/522 ,  H01L29/66 ,  H01L21/762 ,  H01L27/08

CPC classification number: H01L23/5223 ,  H01L29/66181 ,  H01L21/76224 ,  H01L27/0805

Abstract: A semiconductor region includes an isolating region which delimits a working area of the semiconductor region. A trench is located in the working area and further extends into the isolating region. The trench is filled by an electrically conductive central portion that is insulated from the working area by an isolating enclosure. A cover region is positioned to cover at least a first part of the filled trench, wherein the first part is located in the working area. A dielectric layer is in contact with the filled trench. A metal silicide layer is located at least on the electrically conductive central portion of a second part of the filled trench, wherein the second part is not covered by the cover region.

公开(公告)号：US20210159308A1

公开(公告)日：2021-05-27

申请号：US17165013

申请日：2021-02-02

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Abderrezak MARZAKI

IPC: H01L49/02 ,  H01L27/11517 ,  H01L29/06

Abstract: A capacitive element of an integrated circuit includes first and second electrodes. The first electrode is formed by a first electrically conductive layer located above a semiconductor well doped with a first conductivity type. The second electrode is formed by a second electrically conductive layer located above the first electrically conductive layer of the semiconductor well. The second electrode is further formed by a doped surface region within the semiconductor well that is heavily doped with a second conductivity type opposite the first conductivity type, wherein the doped surface region is located under the first electrically conductive layer. An inter-electrode dielectric area electrically separates the first electrode and the second electrode.

公开(公告)号：US20210118725A1

公开(公告)日：2021-04-22

申请号：US17068112

申请日：2020-10-12

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Franck JULIEN ,  Abderrezak MARZAKI

IPC: H01L21/762 ,  H01L21/308 ,  H01L21/311 ,  H01L21/306 ,  H01L21/02 ,  H01L25/18 ,  H01L25/16

Abstract: Trenches of different depths in an integrated circuit are formed by a process utilizes a dry etch. A first stop layer is formed over first and second zones of the substrate. A second stop layer is formed over the first stop layer in only the second zone. A patterned mask defines the locations where the trenches are to be formed. The dry etch uses the mask to etch in the first zone, in a given time, through the first stop layer and then into the substrate down to a first depth to form a first trench. This etch also, at the same time, etch in the second zone through the second stop layer, and further through the first stop layer, and then into the substrate down to a second depth to form a second trench. The second depth is shallower than the first depth.

公开(公告)号：US20210035996A1

公开(公告)日：2021-02-04

申请号：US16939603

申请日：2020-07-27

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Franck JULIEN ,  Abderrezak MARZAKI

IPC: H01L27/11531 ,  H01L27/11521 ,  H01L29/788 ,  H01L21/02 ,  H01L21/311 ,  H01L21/265 ,  H01L21/28 ,  H01L29/66

Abstract: A process for fabricating an integrated circuit includes the fabrication of a first transistor and a floating-gate transistor. The fabrication process for the first transistor and the floating-gate transistor utilizes a common step of forming a dielectric layer. This dielectric layer is configured to form a tunnel-dielectric layer of the floating-gate transistor (which allows transfer of charge via the Fowler-Nordheim effect) and to form a gate-dielectric layer of the first transistor.

公开(公告)号：US20200075506A1

公开(公告)日：2020-03-05

申请号：US16549000

申请日：2019-08-23

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Abderrezak MARZAKI ,  Pascal FORNARA

IPC: H01L23/00 ,  H01L27/01 ,  H01L21/70 ,  G04F1/00

Abstract: An ultralong time constant time measurement device includes elementary capacitive elements that are connected in series. Each elementary capacitive element is formed by a stack of a first conductive region, a dielectric layer having a thickness suited for allowing charge to flow by direct tunneling effect, and a second conductive region. The first conductive region is housed in a trench extending from a front face of a semiconductor substrate down into the semiconductor substrate. The dielectric layer rests on the first face of the semiconductor substrate and in particular on a portion of the first conductive region in the trench. The second conductive region rests on the dielectric layer.

公开(公告)号：US20190287862A1

公开(公告)日：2019-09-19

申请号：US16429836

申请日：2019-06-03

Applicant: STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics (Rousset) SAS

Inventor： Benoit FROMENT ,  Stephan NIEL ,  Arnaud REGNIER ,  Abderrezak MARZAKI

IPC: H01L21/8234 ,  H01L49/02 ,  H01L21/762 ,  H01L27/08 ,  H01C7/12 ,  H01L21/74 ,  H01L29/8605 ,  H01L29/06 ,  H01L23/522 ,  H01L21/765

Abstract: An integrated circuit includes a semiconductor substrate with an electrically isolated semiconductor well. An upper trench isolation extends from a front face of the semiconductor well to a depth located a distance from the bottom of the well. Two additional isolating zones are electrically insulated from the semiconductor well and extending inside the semiconductor well in a first direction and vertically from the front face to the bottom of the semiconductor well. At least one hemmed resistive region is bounded by the two additional isolating zones, the upper trench isolation and the bottom of the semiconductor well. Electrical contacts are electrically coupled to the hemmed resistive region.

公开(公告)号：US20190279947A1

公开(公告)日：2019-09-12

申请号：US16292958

申请日：2019-03-05

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Abderrezak MARZAKI ,  Mathieu LISART

IPC: H01L23/00 ,  H01L27/02 ,  H04N19/44 ,  G06F21/87

Abstract: An integrated circuit includes a first domain supplied with power at a first supply voltage. A first transistor comprising in the first domain includes a first gate region and a first gate dielectric region. A second domain is supply with power at a second supply voltage and includes a second transistor having a second gate region and a second gate dielectric region, the second gate region being biased at a voltage that is higher than the first supply voltage. The first and second gate dielectric regions have the same composition, wherein that composition configures the first transistor in a permanently turned off condition in response to a gate bias voltage lower than or equal to the first supply voltage. The second transistor is a floating gate memory cell transistor, with the second gate dielectric region located between the floating and control gates.