公开(公告)号：US20220140003A1

公开(公告)日：2022-05-05

申请号：US17244212

申请日：2021-04-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wooyoung YANG ,  Bonwon KOO ,  Chungman KIM ,  Kwangmin PARK ,  Hajun SUNG ,  Dongho AHN ,  Changseung LEE ,  Minwoo CHOI

IPC: H01L27/24 ,  H01L27/22 ,  H01L45/00 ,  H01L43/02 ,  H01L43/12

Abstract: A chalcogen compound layer exhibiting ovonic threshold switching characteristics, a switching device, a semiconductor device, and/or a semiconductor apparatus including the same are provided. The switching device and/or the semiconductor device may include two or more chalcogen compound layers having different energy band gaps. Alternatively, the switching device and/or semiconductor device may include a chalcogen compound layer having a concentration gradient of an element of boron (B), aluminum (Al), scandium (Sc), manganese (Mn), strontium (Sr), and/or indium (In) in a thickness direction thereof. The switching device and/or a semiconductor device may exhibit stable switching characteristics while having a low off-current value (leakage current value).

公开(公告)号：US20200227475A1

公开(公告)日：2020-07-16

申请号：US16567094

申请日：2019-09-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jeonghee PARK ,  Dongho AHN ,  Changyup PARK ,  Zhe WU

IPC: H01L27/24 ,  H01L45/00

Abstract: A variable resistance memory device including insulating patterns sequentially stacked on a substrate; first conductive lines between adjacent ones of the insulating patterns and spaced apart from each other in a first direction; a second conductive line between the first conductive lines and penetrating the insulating patterns in a third direction perpendicular to a top surface of the substrate; a phase-change pattern between the second conductive line and each of the first conductive lines and between the adjacent ones of the insulating patterns to cover a top surface of a first adjacent insulating pattern and a bottom surface of a second adjacent insulating pattern; and a selection element between the phase-change pattern and the second conductive line and between the adjacent ones of the insulating patterns to cover the top surface of the first adjacent insulating pattern and the bottom surface of the second adjacent insulating pattern.