REDUNDANT CLOCK TRANSISTION TOLERANT LATCH CIRCUIT
    21.
    发明申请
    REDUNDANT CLOCK TRANSISTION TOLERANT LATCH CIRCUIT 有权
    冗余时钟容许容错电路

    公开(公告)号:US20150123723A1

    公开(公告)日:2015-05-07

    申请号:US14265097

    申请日:2014-04-29

    Applicant: NXP B.V.

    Abstract: Embodiments of a latch circuit and a method of operating a latch circuit are described. In one embodiment, a latch circuit includes an input terminal configured to receive an input data signal, a switching unit configured to control application of the input data signal, a first inverter circuit connected to the switching unit, where the first inverter circuit includes a first cross-coupled pair of inverters, and a second inverter circuit connected to the first inverter circuit through the switching unit. The second inverter circuit includes a second cross-coupled pair of inverters and two transistor devices. Each inverter of the second cross-coupled pair of inverters is connected to a voltage rail through a corresponding transistor device. Each of the two transistor devices is connected to a node that is between the switching unit and the first inverter circuit or the second inverter circuit. Other embodiments are also described.

    Abstract translation: 描述锁存电路的实施例和操作锁存电路的方法。 在一个实施例中,锁存电路包括被配置为接收输入数据信号的输入端子,被配置为控制输入数据信号的应用的开关单元,连接到开关单元的第一反相器电路,其中第一反相器电路包括第一 交叉耦合对的反相器,以及通过开关单元连接到第一反相器电路的第二反相器电路。 第二逆变器电路包括第二交叉耦合的一对反相器和两个晶体管器件。 第二交叉耦合对的反相器的每个反相器通过相应的晶体管器件连接到电压轨。 两个晶体管器件中的每一个连接到开关单元与第一反相器电路或第二反相器电路之间的节点。 还描述了其它实施例。

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