公开(公告)号：US07855866B2

公开(公告)日：2010-12-21

申请号：US11678369

申请日：2007-02-23

申请人： Philip J. Crawley ,  John Camagna ,  Charles Cai

发明人： Philip J. Crawley ,  John Camagna ,  Charles Cai

IPC分类号： H02H9/00

CPC分类号： H04L12/10 ,  H02H3/023 ,  H02H9/041 ,  H04L25/029

摘要： A network interface apparatus is disclosed that includes a connector coupled to a plurality of communication lines. A Physical Layer (PHY) device coupled to the communication lines and to a first ground level. A transient event suppression module coupled between the communication lines and a low impedance path to earth ground. During a transient event the transient event suppression module provides a low impedance path to the earth ground to protect the PHY device from the transient event. A power circuit that delivers power from a second ground level to the PHY device is coupled to the first ground level. The first ground level and the second ground level are coupled to provide a low impedance path during normal operation and high impedance during transient events.

摘要翻译： 公开了一种网络接口设备，其包括耦合到多个通信线路的连接器。 耦合到通信线路和第一地平面的物理层（PHY）设备。 耦合在通信线路和到地面的低阻抗路径之间的瞬态事件抑制模块。 在瞬态事件期间，瞬态事件抑制模块提供到地线的低阻抗路径，以保护PHY器件免受瞬态事件的影响。 将功率从第二接地电平传送到PHY设备的电源电路耦合到第一地电平。 第一接地电平和第二接地电平耦合以在正常操作期间提供低阻抗路径并且在瞬态事件期间提供高阻抗。

公开(公告)号：US06584145B1

公开(公告)日：2003-06-24

申请号：US09324411

申请日：1999-06-02

申请人： John Camagna ,  Tein-Yow Yu ,  James Ward Girardeau, Jr.

发明人： John Camagna ,  Tein-Yow Yu ,  James Ward Girardeau, Jr.

IPC分类号： H03M100

CPC分类号： H03H17/0628 ,  H03H17/0621 ,  H03H2218/10 ,  H04L7/0029

摘要： A converter or a resampler used in a digital communication system converts a first digital signal representing an analog signal into a second digital signal representing the same analog signal. The converter includes a converter filter and a timing circuit. The timing circuit provides a first clock generated from a second clock, and a phase control signal for controlling the conversion of the converter filter. The timing circuit is preferably a numerical controlled oscillator (NCO) and includes an accumulator for generating the first clock from the second clock and a phase offset, and a phase calculator which receives the phase offset to generate a phase control signal. The phase control signal includes a plurality of phase weighting signals, a plurality of control signals, and an interpolation signal. The first digital signal is selectively convoluted with the phase weighting signals, which is controlled by the control signals. The convoluted signals are interpolated by the interpolation signal to generate the second digital signal.

摘要翻译： 在数字通信系统中使用的A转换器或重采样器将表示模拟信号的第一数字信号转换为表示相同模拟信号的第二数字信号。 转换器包括转换器滤波器和定时电路。 定时电路提供从第二时钟产生的第一时钟，以及用于控制转换器滤波器的转换的相位控制信号。 定时电路优选地是数控振荡器（NCO），并且包括用于从第二时钟产生第一时钟和相位偏移的累加器，以及接收相位偏移以产生相位控制信号的相位计算器。 相位控制信号包括多个相位加权信号，多个控制信号和内插信号。 第一数字信号与由控制信号控制的相位加权信号选择性地卷积。 通过内插信号对卷积信号进行内插以产生第二数字信号。