Deposition of tungsten nitride
    21.
    发明授权
    Deposition of tungsten nitride 有权
    沉积氮化钨

    公开(公告)号:US07005372B2

    公开(公告)日:2006-02-28

    申请号:US10690492

    申请日:2003-10-20

    Abstract: Methods for depositing a tungsten nitride layer are described. The methods form a tungsten nitride layer using a carefully controlled deposition technique such as pulsed nucleation layer (PNL). Initially, a tungsten layer is formed on a substrate surface. The tungsten layer is then exposed to a nitriding agent to form a tungsten nitride layer. Methods of forming relatively thick layers of involve repeated cycles of contact with reducing agent, tungsten precursor and nitriding agent. In some cases, the cycle may also include contact with a dopant precursor such as phosphine or arsine.

    Abstract translation: 描述了用于沉积氮化钨层的方法。 该方法使用精心控制的沉积技术如脉冲成核层(PNL)形成氮化钨层。 最初,在衬底表面上形成钨层。 然后将钨层暴露于氮化剂以形成氮化钨层。 形成相对较厚层的方法涉及与还原剂钨前体和氮化剂接触的重复循环。 在一些情况下,该循环还可以包括与诸如膦或胂的掺杂剂前体接触。

    Method and structure for reducing short circuits between overlapping
conductors
    23.
    发明授权
    Method and structure for reducing short circuits between overlapping conductors 失效
    用于减少重叠导体之间的短路的方法和结构

    公开(公告)号:US5751019A

    公开(公告)日:1998-05-12

    申请号:US350763

    申请日:1994-12-06

    Applicant: James A. Fair

    Inventor: James A. Fair

    CPC classification number: H01L27/10852 H01L27/10808 H01L28/40

    Abstract: Method and apparatus for reducing current leakage between overlapping conductive structures in a multi-layered integrated circuit device such as a thin film capacitor is described. A conductive structure operating as a raised lower electrode is preferably fashioned by step-like erosion using a photolithographic techniques atop a dielectric substrate. In accordance with this invention, the dielectric substrate itself is allowed to erode as well to space the conductive structure away from the problemmatic inner corners of the step. By so distancing such conductive structures, like electrodes, from these inside corners, even conventional deposition techniques can be used to fabricate a capacitive device of operational tolerance suitable for DRAM application without risk of unwanted electrode current leakage and possible shorting. By so separating, the capacitance of the device can be reliably increased by increasing the available three dimensional capacitor area and decreasing the film thickness rather than relying primarily on high permittivity dielectrics.

    Abstract translation: 描述了用于减少诸如薄膜电容器的多层集成电路装置中的重叠导电结构之间的电流泄漏的方法和装置。 作为升高的下电极操作的导电结构优选地通过使用电介质基板顶部的光刻技术的阶梯状侵蚀来形成。 根据本发明,允许电介质基板本身也被侵蚀,以使导电结构远离台阶的可疑内角。 通过如此远离这些内角的导电结构(如电极),甚至常规沉积技术也可用于制造适用于DRAM应用的操作公差的电容性器件,而不会有不必要的电极电流泄漏和可能的短路的危险。 通过这样分离,可以通过增加可用的三维电容器面积并减小膜厚度而不是主要依赖于高介电常数电介质来可靠地增加器件的电容。

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