公开(公告)号：US11158536B2

公开(公告)日：2021-10-26

申请号：US16736478

申请日：2020-01-07

Applicant: International Business Machines Corporation

Inventor： Daniel James Dechene ,  Timothy Mathew Philip ,  Somnath Ghosh ,  Robert Robison

IPC: H01L21/033 ,  H01L21/768 ,  H01L21/311

Abstract: A method includes forming a dielectric layer on a semiconductor substrate, forming a hard mask layer on the dielectric layer, forming a sacrificial mandrel layer on the hard mask layer, depositing a sacrificial fill material in an opening in the sacrificial mandrel layer and utilizing the sacrificial fill material to selectively pattern the hard mask layer. The pattern defining first and second spaced openings in the hard mask layer. The method further includes etching the dielectric layer through the first and second openings in the hard mask layer to create first and second trenches in the dielectric layer separated by a dielectric segment of the dielectric layer.

公开(公告)号：US20210280457A1

公开(公告)日：2021-09-09

申请号：US16811291

申请日：2020-03-06

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Timothy Mathew Philip ,  Nicholas Anthony Lanzillo ,  Daniel James Dechene ,  Robert Robison

IPC: H01L21/768 ,  H01L23/522

Abstract: Embodiments of the present invention disclose a method and apparatus for making a multi-layer device comprising a conductive layer, a dielectric layer formed on top of conductive layer, a via pattern formed in the dielectric layer, wherein the via pattern is comprised of a plurality of channels and columns, wherein a first portion of the via pattern downwards extends through the entire dielectric layer to directly contact the conductive layer, wherein a second portion of the via pattern extends downwards without coming into direct contact with the conductive layer.

公开(公告)号：US20210265166A1

公开(公告)日：2021-08-26

申请号：US16795718

申请日：2020-02-20

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Daniel James Dechene ,  Somnath Ghosh ,  Hsueh-Chung Chen ,  Carl Radens ,  Lawrence A. Clevenger

IPC: H01L21/033

Abstract: A method is presented for employing double-patterning to reduce via-to-via spacing. The method includes forming a mandrel layer over a substrate, forming sacrificial hardmask layers over the mandrel layer defining a litho stack, creating a pattern in the litho stack, the pattern having a narrow section connecting two wider sections to define a substantially hour-glass shape, depositing a spacer assuming a shape of the pattern, and etching the litho stack to expose the mandrel layer and metal lines, wherein the metals lines define sharp distal ends reducing a distance between the metal lines.

公开(公告)号：US20210020446A1

公开(公告)日：2021-01-21

申请号：US16514235

申请日：2019-07-17

Applicant: International Business Machines Corporation

Inventor： Stuart Sieg ,  Daniel James Dechene ,  Eric Miller

IPC: H01L21/308 ,  H01L27/092 ,  H01L21/033 ,  H01L21/8234

Abstract: A method of forming a semiconductor structure includes forming a nanosheet stack including alternating layers of a sacrificial material and a channel material over a substrate, the layers of channel material providing nanosheet channels for one or more nanosheet field-effect transistors. The method also includes forming a hard mask stack over the nanosheet stack, and forming a patterning layer over the hard mask stack. The method further includes patterning a lithographic mask over the patterning layer, the lithographic mask defining (i) one or more first regions for direct printing of one or more fins of a first width in the nanosheet stack and the substrate and (ii) one or more second regions for setting the spacing between two or more fins of a second width in the nanosheet stack and the substrate using self-aligned double patterning. The second width is less than the first width.