公开(公告)号：US10467795B2

公开(公告)日：2019-11-05

申请号：US15482724

申请日：2017-04-08

Applicant: Intel Corporation

Inventor： Uzi Sarel ,  Ehud Cohen ,  Tomer Schwartz ,  Amitai Armon ,  Yahav Shadmiy ,  Itamar Ben-Ari ,  Amit Bleiweiss ,  Lev Faivishevsky ,  Tomer Bar-On ,  Yaniv Fais ,  Jacob Subag ,  Michael Behar ,  Guy Jacob ,  Gal Leibovich ,  Jeremie Dreyfuss

IPC: G06N3/04 ,  G06N3/08 ,  G06N3/02 ,  G06T15/00 ,  G06N3/063

Abstract: In an example, an apparatus comprises a plurality of execution units; and logic, at least partially including hardware logic, to determine a sub-graph of a network that can be executed in a frequency domain and apply computations in the sub-graph in the frequency domain. Other embodiments are also disclosed and claimed.

公开(公告)号：US20180314492A1

公开(公告)日：2018-11-01

申请号：US15499893

申请日：2017-04-28

Applicant: Intel Corporation

Inventor： Yaniv Fais ,  Tomer Bar-On ,  Jacob Subag ,  Jeremie Dreyfuss ,  Lev Faivishevsky ,  Michael Behar ,  Amit Bleiweiss ,  Guy Jacob ,  Gal Leibovich ,  Itamar Ben-Ari ,  Galina Ryvchin ,  Eyal Yaacoby

IPC: G06F7/533 ,  G06N99/00

CPC classification number: G06F7/5332 ,  G06N20/00 ,  G06T1/20

Abstract: In an example, an apparatus comprises a plurality of execution units and logic, at least partially including hardware logic, to gate at least one of a multiply unit or an accumulate unit in response to an input of value zero. Other embodiments are also disclosed and claimed.

公开(公告)号：US20180307987A1

公开(公告)日：2018-10-25

申请号：US15494861

申请日：2017-04-24

Applicant: Intel Corporation

Inventor： Amit Bleiweiss ,  Itamar Ben-Ari ,  Michael Behar ,  Guy Jacob ,  Gal Leibovich ,  Jacob Subag ,  Lev Faivishevsky ,  Yaniv Fais ,  Tomer Schwartz

IPC: G06N3/08 ,  G06N5/04 ,  G06N3/04

CPC classification number: G06N3/082 ,  G06F8/52 ,  G06F9/44552 ,  G06N3/04 ,  G06N3/0445 ,  G06N3/0454 ,  G06N3/084 ,  G06N3/105 ,  G06N5/04

Abstract: In an example, an apparatus comprises at least one execution platform; and logic, at least partially including hardware logic, to receive a trained neural network model in a model optimizer and convert the trained neural network model to an optimized model comprising parameters that are fit to the at least one execution platform. Other embodiments are also disclosed and claimed.

公开(公告)号：US10068385B2

公开(公告)日：2018-09-04

申请号：US14969563

申请日：2015-12-15

Applicant: INTEL CORPORATION

Inventor： Amit Bleiweiss ,  Chen Paz ,  Ofir Levy ,  Itamar Ben-Ari ,  Yaron Yanai

IPC: G06T15/50 ,  G06T19/20 ,  G06F17/50 ,  G06N99/00 ,  G06T3/20 ,  G06T3/40 ,  G06T3/60 ,  G06T15/20 ,  G06T17/00 ,  G06K9/00 ,  G06T15/00

Abstract: Techniques are provided for generation of synthetic 3-dimensional object image variations for training of recognition systems. An example system may include an image synthesizing circuit configured to synthesize a 3D image of the object (including color and depth image pairs) based on a 3D model. The system may also include a background scene generator circuit configured to generate a background for each of the rendered image variations. The system may further include an image pose adjustment circuit configured to adjust the orientation and translation of the object for each of the variations. The system may further include an illumination and visual effect adjustment circuit configured to adjust illumination of the object and the background for each of the variations, and to further adjust visual effects of the object and the background for each of the variations based on application of simulated camera parameters.