公开(公告)号：US5646517A

公开(公告)日：1997-07-08

申请号：US561520

申请日：1995-11-22

Applicant: Didier Belot ,  Patrick Bernard

Inventor： Didier Belot ,  Patrick Bernard

IPC: G05F3/30 ,  G05F3/26 ,  G05F3/28 ,  H03F3/343 ,  H03K19/00 ,  G05F3/16

CPC classification number: G05F3/267 ,  Y10S323/907

Abstract: A voltage regulator controls at least one current source of at least one coupled-mode logic gate. The voltage regulator includes a first current source, of a bipolar-type, connected between ground and a first resistor that is connected to a supply voltage. The first current source is controlled by a voltage across a second resistor that is fed by a current from a second current source of a MOS-type. The current value of the second source determines the voltage of an output terminal of the regulator by duplicating this current on a third current source that is mirror-connected to the second source.

Abstract translation: 电压调节器控制至少一个耦合模式逻辑门的至少一个电流源。 电压调节器包括连接在地与连接到电源电压的第一电阻之间的双极型的第一电流源。 第一电流源通过由来自MOS型的第二电流源的电流馈送的第二电阻器的电压控制。 第二个源的当前值通过在镜像连接到第二个源的第三个电流源上复制该电流来确定调节器的输出端子的电压。

公开(公告)号：US20120062288A1

公开(公告)日：2012-03-15

申请号：US13229478

申请日：2011-09-09

Applicant: Didier Belot ,  Pierre-Olivier Lucas De Peslouan ,  Cédric Majek ,  Yann Deval ,  Thierry Taris ,  Jean-Baptiste Begueret

Inventor： Didier Belot ,  Pierre-Olivier Lucas De Peslouan ,  Cédric Majek ,  Yann Deval ,  Thierry Taris ,  Jean-Baptiste Begueret

IPC: H03L7/08

CPC classification number: H03L7/0812 ,  H03L7/0995 ,  H03L7/1974

Abstract: Device for generating a signal of parametrizable frequency comprising a phase locked loop including a generator of a reference signal, a phase-frequency comparator comprising a first input for receiving the reference signal, an oscillator controlled on the basis of the result output by the phase-frequency comparator, a fractional divider coupled between an output of the oscillator and a second input of the phase-frequency comparator, and a selector selectively linking an input of the oscillator either with an input of the generator, or with the output of the oscillator as a function of the multiplication ratio of the fractional divider.

Abstract translation: 用于生成包括参考信号的发生器的锁相环的参数化频率信号的装置，包括用于接收参考信号的第一输入的相位 - 频率比较器，基于由相位信号输出的结果输出的振荡器， 频率比较器，耦合在振荡器的输出和相位 - 频率比较器的第二输入端之间的分数分频器，以及选择器，选择性地将振荡器的输入与发生器的输入或振荡器的输出相连， 分数分频器的倍率的函数。

公开(公告)号：US20100109770A1

公开(公告)日：2010-05-06

申请号：US12523367

申请日：2008-01-14

Applicant: Didier Belot ,  Yann Deval ,  Eric Kerherve ,  Nathalie Deltimple ,  Pierre Jarry

Inventor： Didier Belot ,  Yann Deval ,  Eric Kerherve ,  Nathalie Deltimple ,  Pierre Jarry

IPC: H03G3/20

CPC classification number: H03F1/0266 ,  H03F1/565 ,  H03F3/19 ,  H03F3/217 ,  H03F3/68

Abstract: A reconfigurable power amplifier includes at least one amplification circuit (E1, E2), and a circuit (6) for controlling the amplification circuit so as to adapt its operation according to an applied input signal (RFin). The circuit for controlling includes a circuit (4, 5) for modifying the compression point of the amplification circuit and for adapting the gain of the amplification circuit in such a manner as to increase the power added efficiency of the circuit for the modified compression point.

Abstract translation: 可重构功率放大器包括至少一个放大电路（E1，E2）和用于控制放大电路以便根据所施加的输入信号（RFin）适应其操作的电路（6）。 用于控制的电路包括用于修改放大电路的压缩点并用于调整放大电路的增益的电路（4,5），以增加用于修改的压缩点的电路的功率附加效率。

公开(公告)号：US07623837B2

公开(公告)日：2009-11-24

申请号：US11125291

申请日：2005-05-09

Applicant: Andreia Cathelin ,  Didier Belot

Inventor： Andreia Cathelin ,  Didier Belot

IPC: H04B1/10

CPC classification number: H03H7/0169 ,  H03H9/74 ,  H04B1/28

Abstract: A heterodyne receiving circuit for a digital communication system including a first band pass filter receiving a signal from an antenna, an amplifying circuit and a second narrow band pass filter for selecting one particular channel within a band of frequencies. The two filters are carried out with integrated BAW-type tunable resonators which can be adjusted, respectively, by a first electrical signal and a second electrical signal generated by two PLL-type frequency control loops. The second frequency control loop has a variable division factor for the purpose of selecting one particular channel within said band of frequencies. In addition, the receiving circuit includes a mixer for mixing the signal generated at the output of said second filter with a local oscillation frequency in order to produce an intermediate frequency. The division factor is controlled by a digital processing of the intermediate frequency.

Abstract translation: 一种用于数字通信系统的外差接收电路，包括接收来自天线的信号的第一带通滤波器，放大电路和用于选择频带内的一个特定信道的第二窄带通滤波器。 两个滤波器由集成的BAW型可调谐谐振器进行，分别可以通过由两个PLL型频率控制回路产生的第一电信号和第二电信号来调节。 第二频率控制回路具有可变分频因子，用于选择所述频带内的一个特定信道。 此外，接收电路包括用于将在所述第二滤波器的输出处产生的信号与本地振荡频率混合的混频器，以便产生中频。 分频因子由中频数字处理控制。

公开(公告)号：US20090251235A1

公开(公告)日：2009-10-08

申请号：US12371415

申请日：2009-02-13

Applicant: Didier Belot ,  Alexandre Augusto Shirakawa ,  Eric Kerherve ,  Moustapha El Hassan ,  Yann Deval

Inventor： Didier Belot ,  Alexandre Augusto Shirakawa ,  Eric Kerherve ,  Moustapha El Hassan ,  Yann Deval

IPC: H03H9/02

CPC classification number: H03H9/605 ,  H03H9/542

Abstract: A filtering circuit with BAW type acoustic resonators having at least a first quadripole and a second quadripole connected in cascade, each quadripole having a branch series with a first acoustic resonator of type BAW and a branch parallel with each branch having an acoustic resonator of type BAW, the first acoustic resonator having a frequency of resonance series approximately equal to the frequency of parallel resonance of the second acoustic resonator, the branch parallel of the first quadripole having a first capacitance connected in series with the second resonator and, in parallel with the capacitance, a first switching transistor to short circuit the capacitance.

Abstract translation: 具有至少具有级联连接的第一四极和第二四极的BAW型声谐振器的滤波电路，每个四极具有与BAW类型的第一声谐振器的分支系列和与具有BAW型声谐振器的每个分支并联的分支 所述第一声谐振器具有大致等于所述第二声谐振器的并联谐振频率的共振频率，所述第一四极杆的分支并联具有与所述第二谐振器串联连接的第一电容器，并且与所述电容器 第一个开关晶体管使电容短路。

公开(公告)号：US07382174B2

公开(公告)日：2008-06-03

申请号：US11649341

申请日：2007-01-03

Applicant: Didier Belot ,  Pascal Persechini

Inventor： Didier Belot ,  Pascal Persechini

IPC: H03G3/10 ,  G06G7/24

CPC classification number: H03F1/32 ,  H03F1/302 ,  H03F2200/294 ,  H03F2200/372

Abstract: A transconductor including circuitry for automatically selecting a non-linear class A operation or a linear class AB operation based on an input signal to be processed to generate an output signal, and for automatically adjusting current from a power supply to a level needed for operation of the transconductor.

Abstract translation: 一种跨导体，包括用于基于待处理的输入信号自动选择非线性A类操作或线性AB类操作的电路，以产生输出信号，并且用于自动调节从电源到达操作所需的电平 跨导体。

公开(公告)号：US07224229B2

公开(公告)日：2007-05-29

申请号：US11047475

申请日：2005-01-31

Applicant: Didier Belot

Inventor： Didier Belot

IPC: H03F3/60

CPC classification number: H03F3/607 ,  H03F1/18 ,  H03F2200/294 ,  H03F2200/372

Abstract: An embodiment of an electronic signal amplifier comprises a power source, an input inductor, an output inductor and one or more branches connected in parallel between the terminals of the power source. Each branch comprises a transistor having a control electrode connected to an intermediate terminal of the input inductor, a first main electrode connected to a first terminal of the power source, and a second main electrode connected to a second terminal of the power source via a capacitor. The second main electrode of each transistor of a branch is also connected to an intermediate terminal of the output inductor.

Abstract translation: 电子信号放大器的实施例包括电源，输入电感器，输出电感器以及在电源的端子之间并联连接的一个或多个分支。 每个分支包括具有连接到输入电感器的中间端子的控制电极的晶体管，连接到电源的第一端子的第一主电极和经由电容器连接到电源的第二端子的第二主电极 。 分支的每个晶体管的第二主电极也连接到输出电感器的中间端子。

公开(公告)号：US20060232344A1

公开(公告)日：2006-10-19

申请号：US11400062

申请日：2006-04-07

Applicant: Franck Badets ,  Didier Belot ,  Vincent Lagareste ,  Yann Deval ,  Pierre Melchior ,  Jean-Baptiste Begueret

Inventor： Franck Badets ,  Didier Belot ,  Vincent Lagareste ,  Yann Deval ,  Pierre Melchior ,  Jean-Baptiste Begueret

IPC: H03L7/00

CPC classification number: H03L7/093 ,  H03L7/087 ,  H03L7/0893 ,  H03L7/18 ,  H03L2207/06

Abstract: A phase locked loop includes a controlled oscillator for delivering an output signal at a determined output frequency, and a variable frequency divider for converting the output signal into a signal at divided frequency. The PLL is termed composite in that it includes at least one first loop having a loop filter for generating a first control signal for the oscillator on the basis of the signal at divided frequency, and a second loop having a loop filter, different from the loop filter of the first loop, for generating, on the basis of the signal at divided frequency, a second signal for additional control of the oscillator. The loop filter of the first loop and the loop filter of the second loop have different respective cutoff frequencies. The passband of the first loop, can be adapted to ensure the convergence and the stability of the PLL, while the second loop can afford extra passband increasing the speed of adaptation of the PLL in case of modification of the value of a preset for the output frequency.

Abstract translation: 锁相环包括用于以确定的输出频率输出输出信号的受控振荡器和用于将输出信号转换为分频的信号的可变分频器。 PLL被称为复合，因为它包括至少一个具有环路滤波器的第一环路，该环路滤波器基于分频频率的信号产生用于振荡器的第一控制信号，以及具有不同于环路的环路滤波器的第二环路 滤波器，用于基于分频后的信号产生用于对振荡器进行附加控制的第二信号。 第一回路的环路滤波器和第二回路的环路滤波器具有不同的各自的截止频率。 第一个环路的通带可以适应于确保PLL的收敛和稳定性，而第二个环路可以提供额外的通带，在修改输出预置值的情况下可以提高PLL的自适应速度 频率。

公开(公告)号：US07110741B2

公开(公告)日：2006-09-19

申请号：US10722245

申请日：2003-11-25

Applicant: Vincent Knopik ,  Didier Belot

Inventor： Vincent Knopik ,  Didier Belot

IPC: H04B1/28

CPC classification number: H01Q23/00 ,  H01Q9/04

Abstract: A radiofrequency unit comprising a first dielectric substrate supporting a first conductive antenna layer; a second dielectric substrate supporting circuit elements connected or coupled to ground formed in a second conductive layer, and comprising a radiofrequency antenna line; and a third screen conductive layer arranged between the first and second substrates, provided with a slot to couple the antenna line to the antenna layer, this conductive layer being floating; in which the thickness and the nature of the second substrate are chosen by taking into account the surface of said circuit elements for the screen layer to be coupled to ground by a capacitor forming a short-circuit for radiofrequencies.

Abstract translation: 一种射频单元，包括支撑第一导电天线层的第一电介质基片; 第二电介质基板，支撑连接或耦合到形成在第二导电层中的地面的电路元件，并且包括射频天线线; 以及布置在第一和第二基板之间的第三屏幕导电层，设置有用于将天线线耦合到天线层的槽，该导电层是浮动的; 其中通过考虑用于形成用于射频的短路的电容器耦合到地的屏蔽层的所述电路元件的表面来选择第二衬底的厚度和性质。

公开(公告)号：US06882194B2

公开(公告)日：2005-04-19

申请号：US10367195

申请日：2003-02-14

Applicant: Didier Belot ,  Pascal Persechini

Inventor： Didier Belot ,  Pascal Persechini

IPC: G06G7/12 ,  G06G7/16 ,  H03D7/12 ,  H03D7/14 ,  H04B1/707

CPC classification number: H03D7/1425 ,  H03D7/1433 ,  H03D7/1491 ,  H03D2200/0043

Abstract: A differential mixer including at least two input/output stages, each stage including two identical branches, each branch of one of the two stages including at least two bipolar transistors the bases of which define a first pair of input/output terminals of the stage and are connected to a same D.C. current source individually by a respective isolating resistor; the collectors of which define a second pair of input/output terminals of the stage which forms a pair of input/output terminals of another stage of the mixer; and the emitters of which are individually connected to a low voltage reference line by a respective degenerative impedance.

Abstract translation: 包括至少两个输入/输出级的差分混频器，每个级包括两个相同的分支，两级中的一个的每个分支包括至少两个双极型晶体管，其基准基底限定了该级的第一对输入/输出端子，以及 通过相应的隔离电阻器分别连接到相同的DC电流源; 其集电器限定了级的第二对输入/输出端子，其形成混频器的另一级的一对输入/输出端子; 并且其发射极通过相应的退化阻抗单独地连接到低电压参考线。