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公开(公告)号：US10797651B2
公开(公告)日：2020-10-06
申请号：US16348824
申请日：2018-04-27
Inventor： Graeme Gordon Mackay , Lei Zhu , Ku He , Vamsikrishna Parupalli
Abstract: In accordance with embodiments of the present disclosure, a method for power supply rejection for an amplifier may include generating a correction signal by multiplying a quantity indicative of a power supply voltage of the amplifier by a transfer function defining a response from the power supply voltage of the amplifier to an output signal of the amplifier and subtracting the correction signal from a signal within a signal path of a circuit comprising the amplifier.
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公开(公告)号：US10727860B1
公开(公告)日：2020-07-28
申请号：US16522033
申请日：2019-07-25
Inventor： Wai-Shun Shum , Lei Zhu , Johann G. Gaboriau , Xiaofan Fei , Xin Zhao
IPC: H03M3/00
Abstract: A digital delta-sigma modulator may include a loop filter having a loop filter input configured to receive an input signal and generate an intermediate signal responsive to the input signal and a multi-bit quantizer configured to quantize the intermediate signal into a quantized output signal which is fed back as an input to the loop filter. The multi-bit quantizer may further be configured to operate in at least two modes comprising: (a) a normal mode in which, for each sample of the intermediate signal, the multi-bit quantizer generates a corresponding sample having a value selected from a set of a plurality of quantization levels; and (b) a code suppression mode in which, for each sample of the intermediate signal, the multi-bit quantizer generates a corresponding sample having a value selected from a subset of the set of a plurality of quantization levels.
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公开(公告)号：US10404248B2
公开(公告)日：2019-09-03
申请号：US16219187
申请日：2018-12-13
Inventor： Tejasvi Das , Alan Mark Morton , Xin Zhao , Lei Zhu , Xiaofan Fei , Johann G. Gaboriau , John L. Melanson , Amar Vellanki
Abstract: A system may include a digital pulse width modulator subsystem, a first path coupled to an output of the digital pulse width modulator subsystem and configured to drive an open-loop driver stage, a second path coupled to the output of the digital pulse width modulator subsystem and configured to drive a closed-loop analog pulse width modulator, a controller to select between the first path and the second path for processing a signal based on one or more characteristics of the signal, and a calibration subsystem configured to calibrate at least one of a first gain of the first path and a second gain of the second path in order that the first gain and the second gain are at least approximately equal at the time of switching selection between the first path and the second path or vice versa, in order to minimize artifacts due to the switching.
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公开(公告)号：US10320337B2
公开(公告)日：2019-06-11
申请号：US15418405
申请日：2017-01-27
Inventor： Xin Zhao , Tejasvi Das , Hossein Mirzaie , Lei Zhu , Xiaofan Fei
Abstract: A dynamic common reference input (CMRI) signal may be provided to an operational amplifier, or “op-amp,” in an amplifier system to reduce the common mode ripple of the fully-differential op-amp, while adding little or no noise in the amplifier system. The dynamic CMRI signal may be controlled such that a common-mode component of two amplifier input nodes of the operational amplifier is made approximately independent of two input signals received at two system input nodes of the amplifier system. An amplifier system with the dynamic CMRI may be used in class-D amplifiers, such as amplifiers for audio systems that generate output for headphones or speakers.
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公开(公告)号：US09917557B1
公开(公告)日：2018-03-13
申请号：US15488979
申请日：2017-04-17
Inventor： Lei Zhu , Xin Zhao , Tejasvi Das , Alan Mark Morton , Xiaofan Fei
CPC classification number: H03F3/2178 , H03F1/0277 , H03F3/187 , H03F3/211 , H03F3/2171 , H03F3/72 , H03F2200/03 , H03F2200/321 , H03F2200/375 , H03F2200/411
Abstract: A method for offset calibration may include decoupling a modulator input of a first path from a first stage output, coupling a second path output to the modulator input, applying a common-mode voltage to a second path input, receiving a calibration signal from the modulator output generated in response to the common-mode voltage, and modifying one or more parameters of the modulator to compensate for an offset between the first path and the second path indicated by the calibration signal. A method for gain calibration may include decoupling a modulator input from a first stage output, decoupling a second path from the first stage output, applying a first test signal to the modulator input, applying a second test signal to a second path input, wherein the second test signal is of opposite phase as the first test signal, coupling a second path output to an amplifier input via a calibration feedback network, receiving a calibration signal from the first stage output generated in response to the first test signal and the second test signal, and modifying one or more parameters of the second path to compensate for a difference in respective gains of the modulator and the second path indicated by the calibration signal.
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Patent Agency Ranking
公开(公告)号：US11271583B2
公开(公告)日：2022-03-08
申请号：US16945288
申请日：2020-07-31
Inventor： John L. Melanson , Johann G. Gaboriau , Lei Zhu , Wai-Shun Shum , Xiaofan Fei , Leyi Yin
Abstract: A differential output current digital-to-analog converter (IDAC) circuit may include a delta-sigma modulator configured to receive a digital input signal, a control circuit responsive to the delta-sigma modulator configured to perform a DAC decode operation, a plurality of DAC elements responsive to the DAC decode operation, the plurality of DAC elements configured to, in concert, generate a differential output current signal based on the digital input signal to a load coupled to a pair of output terminals of the IDAC, and an output impedance coupled between the pair of output terminals such that the output impedance is in parallel with the load.
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公开(公告)号：US11190168B2
公开(公告)日：2021-11-30
申请号：US16784392
申请日：2020-02-07
Inventor： Jing Bai , Tejasvi Das , Xin Zhao , Lei Zhu , Xiaofan Fei
IPC: H03K17/687 , H03K3/01 , H03K19/0185 , H03K19/0175 , H04R3/00
Abstract: A driver system may include a first n-type field-effect transistor coupled at its non-gate terminals between an output of the driver system and a first terminal of a supply voltage and configured to drive the output when the first n-type field-effect transistor is activated, a second n-type field-effect transistor coupled at its non-gate terminals between an output of the driver system and a second terminal of the supply voltage and configured to drive the output when the second n-type field-effect transistor is activated, a high-side capacitor coupled to the output of the driver system, and a low-side capacitor coupled to the second terminal of the supply voltage, wherein the high-side capacitor and the low-side capacitor are configured to track and correct for mismatches between a first resistance of the first n-type field-effect transistor and a second resistance of the second n-type field-effect transistor.
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公开(公告)号：US11070203B2
公开(公告)日：2021-07-20
申请号：US16162960
申请日：2018-10-17
Inventor： Jing Bai , Tejasvi Das , Xin Zhao , Lei Zhu , Xiaofan Fei
IPC: H03K17/687 , G06F3/01 , H03K17/06 , H03K19/0175 , H03K19/0185 , H03F3/217 , H03F3/183 , H04R3/12
Abstract: A driver system may include a first n-type field-effect transistor coupled at its non-gate terminals between an output of the driver system and a first terminal of a supply voltage and configured to drive the output when the first n-type field-effect transistor is activated, a second n-type field-effect transistor coupled at its non-gate terminals between an output of the driver system and a second terminal of the supply voltage and configured to drive the output when the second n-type field-effect transistor is activated, a high-side capacitor coupled to the output of the driver system, and a low-side capacitor coupled to the second terminal of the supply voltage, wherein the high-side capacitor and the low-side capacitor are configured to track and correct for mismatches between a first resistance of the first n-type field-effect transistor and a second resistance of the second n-type field-effect transistor.
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公开(公告)号：US10164590B2
公开(公告)日：2018-12-25
申请号：US15910774
申请日：2018-03-02
Inventor： Lingli Zhang , Yongjie Cheng , Lei Zhu , Christian Larsen , John L. Melanson
Abstract: An improved Class-D amplifier may include a digital PWM modulator that receives a digital audio signal and that provides a PWM signal as an input to an analog PWM modulator of the Class-D amplifier. A digital PWM modulator may be configured to receive a digital signal and to generate a first PWM signal based on the digital signal. A digital PWM driver may be coupled to the digital PWM modulator. The digital PWM driver may be configured to receive the first PWM signal and to generate a reference PWM signal based on the first PWM signal. An analog PWM modulator may be coupled to the digital PWM driver. The analog PWM modulator may be configured to receive the reference PWM signal and to generate an output PWM signal based on the reference PWM signal.
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公开(公告)号：US20180254757A1
公开(公告)日：2018-09-06
申请号：US15910774
申请日：2018-03-02
Inventor： Lingli Zhang , Frank Cheng , Lei Zhu , Christian Larsen , John L. Melanson
CPC classification number: H03F3/217 , H03F3/183 , H03F3/2171 , H03F3/2175 , H03F2200/03 , H03F2200/351
Abstract: An improved Class-D amplifier may include a digital PWM modulator that receives a digital audio signal and that provides a PWM signal as an input to an analog PWM modulator of the Class-D amplifier. A digital PWM modulator may be configured to receive a digital signal and to generate a first PWM signal based on the digital signal. A digital PWM driver may be coupled to the digital PWM modulator. The digital PWM driver may be configured to receive the first PWM signal and to generate a reference PWM signal based on the first PWM signal. An analog PWM modulator may be coupled to the digital PWM driver. The analog PWM modulator may be configured to receive the reference PWM signal and to generate an output PWM signal based on the reference PWM signal.
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