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公开(公告)号：US20180197495A1
公开(公告)日：2018-07-12
申请号：US15534195
申请日：2016-12-22
Inventor： Zhuo Xu , Rui Wang , Yajie Bai , Jaikwang Kim , Fei Shang , Haijun Qiu
IPC: G09G3/36 , H01L27/12 , G09G3/3225
CPC classification number: G09G3/3655 , G02F1/134336 , G02F1/1362 , G02F1/13624 , G02F1/136286 , G02F1/1368 , G09G3/3225 , G09G3/3614 , G09G3/3648 , G09G2300/0426 , G09G2300/0439 , G09G2300/0861 , G09G2310/0251 , G09G2320/0204 , G09G2330/021 , G09G2340/0407 , H01L27/12 , H01L27/124 , H01L27/3276 , H01L51/5206
Abstract: The present application discloses an array substrate, a driving method thereof, and related display apparatus based on an improved dual-gate scheme. The array substrate includes multiple groups each having two columns of pixel electrodes without laying a data line in a gap between the two columns. Each group includes multiple second transistors for pre-charging respective pairs of pixel electrodes having reversed polarities in each corresponding scanning cycle. Before each pixel electrode is charged via a first transistor, turning on the second transistor allows charge sharing between the two pixel electrodes having reversed polarities so that the charging time of each pixel electrodes is substantially reduced and the operation power is saved.
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公开(公告)号：US09735278B2
公开(公告)日：2017-08-15
申请号：US14744557
申请日：2015-06-19
Inventor： Wu Wang , Haijun Qiu , Fei Shang , Guolei Wang
IPC: H01L27/12 , H01L29/786
CPC classification number: H01L29/78642 , H01L27/1222
Abstract: An array substrate, a display panel and a method of manufacturing a thin film transistor (TFT) are provided. The array substrate includes a base substrate and a thin film transistor (TFT) formed on the base substrate, and the TFT includes a gate electrode, a gate insulating layer, an active layer, source/drain electrodes and an interlayer insulating layer. The source/drain electrodes include a first electrode and a second electrode, and the interlayer insulating layer is located between the first electrode and the second electrode. The gate electrode, the gate insulating layer and the active layer are arranged sequentially in a direction perpendicular to a thickness direction of the array substrate, and the first electrode, the interlayer insulating layer and the second electrode are arranged sequentially in the thickness direction of the array substrate.
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公开(公告)号：US12289954B2
公开(公告)日：2025-04-29
申请号：US17356364
申请日：2021-06-23
Inventor： Jibum Yang , Euiku Lee , Myoungsoo Lee , Chao Kong , Lin Guo , Na Li , Haijun Qiu
IPC: H10K59/12 , H10K50/86 , H10K59/122 , H10K71/00 , H10K59/38
Abstract: Disclosed are a display panel, a manufacturing method thereof and a displaying device. The display panel comprises a driving backplane, a light-emitting device layer disposed on the driving backplane, and an encapsulation layer, a color film layer and a color separation suppression layer which are disposed on the side, away from the driving backplane, of the light-emitting device layer, wherein the color separation suppression layer is configured to interfere with and cancel out external ambient light, so as to reduce the external ambient light incident on the light-emitting device layer and the driving backplane and block the external ambient light reflected by the light-emitting device layer and the driving backplane from exiting from a light-exiting surface of the display panel.
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公开(公告)号：US12266308B2
公开(公告)日：2025-04-01
申请号：US18669642
申请日：2024-05-21
Inventor： Rui Wang , Ming Hu , Haijun Qiu , Weiyun Huang , Yao Huang , Chao Zeng , Yuanyou Qiu , Shaoru Li , Tianyi Cheng
IPC: G09G3/3233
Abstract: A pixel circuit and a driving method thereof, and a display device are provided. The pixel circuit includes a driving sub-circuit, a data writing sub-circuit, a first light-emitting control sub-circuit, a second light-emitting control sub-circuit, a compensation sub-circuit, and a first reset sub-circuit, and is configured to generate a driving current to control a light-emitting element to emit light, the first reset sub-circuit comprises a first transistor, the compensation sub-circuit comprises a second transistor, the first transistor and the second transistor are both polysilicon oxide thin film transistors, and an active layer type of the first transistor and an active layer type of the second transistor are different from an active layer type of a transistor comprised in at least one selected from a group consisting of the driving sub-circuit, the data writing sub-circuit, the first light-emitting control sub-circuit, and the second light-emitting control sub-circuit.
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公开(公告)号：US20250107362A1
公开(公告)日：2025-03-27
申请号：US18727637
申请日：2023-03-30
Inventor： Mengqi Wang , Ziyang Yu , Zhiliang Jiang , Rong Wang , Ming Hu , Haijun Qiu , Xiangdan Dong , Jun Yan , Fan He
IPC: H10K59/131
Abstract: A display substrate has a fan-out area and includes a plurality of conductive layers. The plurality of conductive layers include data lines, connection lines and fan-out lines. A connection line is electrically connected to a first data line, and crosses at least one data line and is insulated from the crossed data line. A first fan-out line is electrically connected to the connection line. A second fan-out line is electrically connected to a second data line. The first fan-out line includes a transfer line, and is located in a different conductive layer from second fan-out lines and crosses at least one second fan-out line. An order of arrangement of ends of the fan-out lines away from the display area in a first direction is same as an order of arrangement of the data lines in the first direction.
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Patent Agency Ranking
公开(公告)号：US12260816B2
公开(公告)日：2025-03-25
申请号：US18017234
申请日：2022-01-29
Inventor： Yi Zhang , Ming Hu , Huijuan Yang , Tingliang Liu , Kai Zhang , Haijun Qiu , Youngyik Ko , Tinghua Shang , Biao Liu
IPC: G09G3/3233
Abstract: Provided are a pixel circuit, a driving method and a display apparatus, including: a light emitting device; a driving transistor, configured to produce a current for driving the light emitting device to emit light according to a data voltage; a voltage control circuit, coupled to the driving transistor, wherein the voltage control circuit is configured to reset the driving transistor (M0) and input the data voltage in response to a loaded signal; and a light emitting control circuit, coupled to the driving transistor and the light emitting device, wherein the light emitting control circuit is configured to provide the current produced by the driving transistor to the light emitting device; wherein a frequency of resetting the driving transistor is not less than a frequency of inputting the data voltage.
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公开(公告)号：US20250087163A1
公开(公告)日：2025-03-13
申请号：US18288412
申请日：2022-12-19
Inventor： Ziyang Yu , Haijun Qiu , Ming Hu , Zhiliang Jiang , Tianyi Cheng , Jianpeng Wu , Erjin Zhao , Mengqi Wang , Wenbo Chen , Cong Liu , Qian Xu
IPC: G09G3/3266 , G09G3/3258
Abstract: A driving circuit includes a driving signal generation circuit, a gating circuit, an output control circuit, an output circuit and a voltage control circuit; the driving signal generation circuit generates an Nth stage of driving signal, the output control circuit connects the first control node and the second node under the control of the potential of the first node; the gating circuit controls to write a gating input signal into the first node under the control of a gating control signal; the voltage control circuit controls a potential of the second node according to a potential of the first node; the output circuit connects the output driving terminal and the first voltage terminal under the control of the potential of the second node, and connects the output driving terminal and the second voltage terminal under the control of the potential of the third control node.
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公开(公告)号：US20250078739A1
公开(公告)日：2025-03-06
申请号：US18287520
申请日：2022-12-19
Inventor： Ziyang Yu , Haijun Qiu , Ming Hu , Zhiliang Jiang , Tianyi Cheng , Jianpeng Wu , Qingqing Yan , Xiangnan Pan , Qing He , Quanyong Gu , Sifei Ai , Junhao Jing , Xiang Luo
IPC: G09G3/3225
Abstract: A driving circuit includes a driving signal generation circuit, a gating circuit, an output control circuit, a voltage control circuit and an output circuit; the driving signal generation circuit generates the Nth stage of driving signal; the gating circuit writes a gating input signal into the first node under the control of a gating control signal; the output control circuit connects the first control node and the second node under the control of a potential of the first node; the voltage control circuit controls a potential of the second node according to the potential of the first node; the output circuit connects the output driving terminal and the first voltage terminal under the control of the potential of the second node, and connects the output driving terminal and the second voltage terminal under the control of the potential of the second control node; N is a positive integer.
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29.发明授权公开(公告)号：US11974484B2
公开(公告)日：2024-04-30
申请号：US18204372
申请日：2023-05-31
Inventor： Haijun Qiu , Yangpeng Wang , Benlian Wang , Haijun Yin , Yang Wang , Yao Hu , Weinan Dai
CPC classification number: H10K59/353 , H10K59/352 , H10K71/00 , H10K71/164 , H10K71/166
Abstract: A pixel arrangement structure includes: first sub-pixels, second sub-pixels and third sub-pixels, being not overlapped but being spaced apart. The third sub-pixel includes a first edge facing the first sub-pixel, the first sub-pixel includes a second edge facing the third sub-pixel, the third sub-pixel includes a third edge facing the second sub-pixel, and the second sub-pixel includes a fourth edge facing the third sub-pixel, and shapes of the first sub-pixel and the second sub-pixel are circles, the first edge and the second edge are curved edges with a same curvature, the third edge and the fourth edge are curved edges with a same curvature; or shapes of the first sub-pixel and the second sub-pixel are octagons, at least part of the first edge is parallel to at least part of the second edge, at least part of the third edge is parallel to at least part of the fourth edge.
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30.发明申请公开(公告)号：US20220165810A1
公开(公告)日：2022-05-26
申请号：US17650374
申请日：2022-02-08
Inventor： Haijun Qiu , Yangpeng Wang , Benlian Wang , Haijun Yin , Yang Wang , Yao Hu , Weinan Dai
Abstract: A pixel arrangement structure includes: first sub-pixels, second sub-pixels and third sub-pixels, all being not overlapped but being spaced apart. The third sub-pixels have a first symmetry axis and a second symmetry axis that are perpendicular to each other. The first symmetry axis extends through a geometric center of a respective first sub-pixel adjacent to a respective third sub-pixel of the plurality of third sub-pixels, intersects a first edge of the respective third sub-pixel at a first intersection point, and intersects a second edge of the adjacent respective first sub-pixel at a second intersection point. A distance between the first intersection point and the second intersection point is a minimum distance between the respective third sub-pixel and the respective first sub-pixel. The second symmetry axis is similarly configured with respect to a respective second sub-pixel and the respective third sub-pixel.
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