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公开(公告)号：US20230343287A1
公开(公告)日：2023-10-26
申请号：US18044114
申请日：2021-02-07
Inventor： Hongfei CHENG , Xueguang HAO
IPC: G09G3/3233
CPC classification number: G09G3/3233 , G09G2300/0819 , G09G2300/0852 , G09G2300/0861 , G09G2310/08 , G09G2320/0223 , G09G2320/0233 , G09G2320/045
Abstract: Embodiments of the present disclosure provide a pixel circuitry, a drive method thereof, an array substrate and a display panel. The pixel circuitry may comprise a drive circuit, a data write circuit, an initialization circuit, a first light emission control circuit, a first storage circuit, a second storage circuit and a second light emission control circuit. The drive circuit may be coupled to a first node, a second node and a third node, and may provide a drive current to a light emitting device. The first storage circuit may store a voltage difference between the first voltage signal terminal and the second node. The second storage circuit may store a voltage difference between the first node and the second node.
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公开(公告)号：US20210399061A1
公开(公告)日：2021-12-23
申请号：US16908935
申请日：2020-06-23
Inventor： Fengli JI , Hongli WANG , Xueguang HAO
IPC: H01L27/32
Abstract: A pixel arrangement structure, a display substrate and a mask group are disclosed. The pixel arrangement structure includes a plurality of pixel groups, each of the plurality of pixel groups includes one red sub-pixel, two green sub-pixels and one blue sub-pixel; the red sub-pixel and the blue sub-pixel are arranged along a first direction; the two green sub-pixels are arranged along a second direction. Four vertexes included in the red sub-pixel are located in a first virtual rhombus and are substantially coincident with four vertexes of the first virtual rhombus, respectively; four vertexes included in the blue sub-pixel are located in a second virtual rhombus and are substantially coincident with four vertexes of the second virtual rhombus, respectively; at least one of the red or the blue sub-pixel has a shape of a corresponding virtual rhombus with each side of the virtual rhombus being an inwardly concaved side.
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公开(公告)号：US20210036083A1
公开(公告)日：2021-02-04
申请号：US16342039
申请日：2018-08-30
Applicant: BOE Technology Group Co., Ltd.
Inventor： Xueguang HAO , Xinyin WU , Yongda MA
IPC: H01L27/32 , G09G3/3233
Abstract: The disclosure discloses a pixel circuit, a display panel, and a display device. The display device comprises: a light emitting device with a second terminal coupled to a low voltage signal line; a drive thin film transistor with a second terminal coupled to a first terminal of the light emitting device; a light emitting control thin film transistor with a first terminal coupled to a high voltage signal line, and a second terminal coupled to a first terminal of the drive thin film transistor; a switch thin film transistor, which controls data voltage to be written into a control terminal of the drive thin film transistor; a reset thin film transistor, which resets potential of the control terminal of the drive thin film transistor; and a storage capacitor, coupled to the control terminal and the second terminal of the drive thin film transistor.
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公开(公告)号：US20210013293A1
公开(公告)日：2021-01-14
申请号：US17032110
申请日：2020-09-25
Inventor： Xueguang HAO , Fang LIU , Bo ZHANG
Abstract: The disclosure relates to a display panel and a display apparatus. The display panel comprises: a substrate comprising a substrate display region corresponding to a display panel display region and a substrate non-display region corresponding to a display panel non-display region; a non-display region circuit located at the substrate non-display region; and a packaging layer located on the non-display region circuit and having at least a partial overlap area with the non-display region circuit, wherein the non-display region circuit comprises: a first conductive pattern; at least one buffer layer located at a side of the first conductive pattern close to the substrate; at least one gate insulating layer configured to electrically insulate the first conductive pattern and other conductive patterns; and at least one interlayer insulating layer located at a side of the first conductive pattern away from the substrate.
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公开(公告)号：US20200227498A1
公开(公告)日：2020-07-16
申请号：US16475335
申请日：2018-10-24
Applicant: BOE TECHNOLOGY GROUP CO., LTD.
Inventor： Hongfei CHENG , Yuxin ZHANG , Xueguang HAO , Yongda MA , Yongchun LU , Hui LI
Abstract: An array substrate, a display panel and a display device are provided. The array substrate includes a plurality of pixel units, wherein each pixel unit includes a storage capacitor including at least three electrode plates parallel to each other, the at least three electrode plates parallel to each other include a first electrode plate, a second electrode plate and a third electrode plate, the first electrode plate is electrically connected to the second electrode plate, the third electrode plate is disposed between the first electrode plate and the second electrode plate, and the first electrode plate and the second electrode plate each have a portion facing towards the third electrode plate.
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Patent Agency Ranking
公开(公告)号：US20190079326A1
公开(公告)日：2019-03-14
申请号：US15909730
申请日：2018-03-01
Applicant: BOE Technology Group Co., Ltd.
Inventor： Xueguang HAO , Yong QIAO , Xinyin WU
CPC classification number: G02F1/13306 , G09G3/36 , G09G3/3614 , G09G2300/04 , G09G2330/021
Abstract: The disclosure discloses an array substrate, a method for controlling the same, a display panel and a display device. The array substrate includes data lines, a control circuit, a discharge circuit, a control signal terminal and a voltage output circuit; the control circuit is configured to control an operation of the discharge circuit; the voltage output circuit is configured to output a preset voltage signal with a voltage value between grayscale voltage with positive and negative polarities required for the array substrate; and the discharge circuit is configured to be controlled by the control circuit, in a period of time between two adjacent frames of images being displayed, to control the data lines to be electrically connected with the voltage output circuit, and in a period of time of any one frame of image being displayed, to control the data lines to be electrically disconnected with the voltage output circuit.
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公开(公告)号：US20180315774A1
公开(公告)日：2018-11-01
申请号：US15743530
申请日：2017-07-14
Applicant: BOE TECHNOLOGY GROUP CO., LTD.
Inventor： Jianbo XIAN , Xueguang HAO , Hongfei CHENG , Yongda MA
IPC: H01L27/12 , G02F1/1362
CPC classification number: H01L27/124 , G02F1/136259 , G02F1/136286 , G02F2001/136263 , G02F2001/136272
Abstract: An embodiment of the present disclosure relates to an array substrate, which comprises data lines and gate lines arranged on the array substrate having a pixel region and a peripheral region surrounding the pixel region, and at least two repair lines arranged on the peripheral region of the array substrate. The at least two repair lines intersect with one of the data lines and the gate lines. Each of the repair lines has at least one repair voltage lead. The array substrate according to the present disclosure can increase the number of data lines or gate lines that can be repaired, improve a utilization ratio of the repair lines, and can be used for repairing a display panel with large area.
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公开(公告)号：US20180114936A1
公开(公告)日：2018-04-26
申请号：US15535880
申请日：2016-07-13
Applicant: BOE TECHNOLOGY GROUP CO., LTD.
Inventor： Xueguang HAO , Hongfei CHENG , Yong QIAO , Xinyin WU
CPC classification number: H01L51/502 , H01L27/32 , H01L33/06 , H01L51/50 , H01L51/5004 , H01L51/5056 , H01L51/5072 , H01L51/56 , H01L2251/5369 , H01L2251/552
Abstract: A quantum dot electroluminescent device and a display apparatus are provided. The quantum dot electroluminescent device includes: a first electrode, an electron transport layer, a quantum dot luminescent layer, a hole transport layer and a second electrode, wherein the quantum dot luminescent layer is disposed between the electron transport layer and the hole transport layer; the quantum dot luminescent layer includes a base material layer and a quantum dot luminescent material which is dispersed in the base material layer; a highest occupied molecular orbital energy level of the base material layer is between a highest occupied molecular orbital energy level of the hole transport layer and a highest occupied molecular orbital energy level of the quantum dot luminescent material.
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公开(公告)号：US20180108676A1
公开(公告)日：2018-04-19
申请号：US15525622
申请日：2016-06-03
Applicant: BOE TECHNOLOGY GROUP CO., LTD.
Inventor： Hongfei CHENG , Jianbo XIAN , Pan LI , Xueguang HAO
IPC: H01L27/12 , H01L27/32 , H01L33/00 , H01L51/52 , G02F1/1362 , H01L29/786
CPC classification number: H01L27/124 , G02F1/1362 , G02F1/136286 , G02F1/1368 , H01L27/1222 , H01L27/3276 , H01L29/7869 , H01L33/0041 , H01L51/5284
Abstract: An array substrate, a method of manufacturing the same, and a display device are provided. In the array substrate of the present disclosure, the gate cutout is formed in the area where the gate line intersects the data line. The array substrate can reduce the coupling capacitance between the data line and the gate line. When the gate cutout extends beyond the area between the first thin film transistor and the second thin film transistor, the mutual interference between two thin film transistors of each pixel region can be further reduced.
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公开(公告)号：US20180031928A1
公开(公告)日：2018-02-01
申请号：US15650486
申请日：2017-07-14
Applicant: BOE TECHNOLOGY GROUP CO., LTD.
Inventor： Xueguang HAO , Jianbo XIAN , Yong QIAO
IPC: G02F1/1343 , H01L21/768 , H01L21/77 , G09G3/36 , H01L27/12 , G02F1/1362
Abstract: The present disclosure provides an array substrate, a driving method thereof and a display panel. The array substrate includes: a plurality of pixels arranged in a matrix, wherein two adjacent rows of pixels are grouped into a pixel group; switching elements respectively connected with the pixels; a data line, wherein two data lines corresponds to each column of pixels arranged at two sides of this column respectively; and gate lines each located between two adjacent rows of pixels of each pixel group; wherein respective pixels in a same pixel group are connected with one gate line located between two rows of pixels though respective switching elements; two pixels adjacent to each other along a column direction in a same pixel group are respectively connected with two data lines respectively located at two sides of a column where the two pixels are located through respective switching elements.
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