公开(公告)号：US06239009B1

公开(公告)日：2001-05-29

申请号：US09409677

申请日：1999-09-30

申请人： Jong Moo Choi ,  Sung Ryul Kim ,  Young Keun Park

发明人： Jong Moo Choi ,  Sung Ryul Kim ,  Young Keun Park

IPC分类号： H01L213205

CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L29/66825

摘要： A flash memory device has improved erasable characteristics and device reliability. The flash memory device includes a semiconductor substrate and heavily doped impurity regions formed spaced apart from one another by a predetermined distance in the semiconductor substrate in a first direction. First and second isolation regions are formed spaced apart from each other by a second predetermined distance on the semiconductor substrate, in a second direction which is preferably at a right angle to the first direction. Each of the floating gates are formed between the first and second isolation regons and between the heavily doped impurity regions. The control gate lines are formed between the first and second isolation regions, and over the floating gates in the same direction as the first and second isolation regions. An erase gate line is formed to have a narrower width than the floating gate, and is formed over the floating gate, preferably at a right angle to the control gate line.

摘要翻译： 闪存器件具有改进的可擦除特性和器件可靠性。 闪速存储器件包括在第一方向上在半导体衬底中彼此间隔开预定距离形成的半导体衬底和重掺杂杂质区。 第一隔离区域和第二隔离区域在第二方向上在半导体衬底上彼此间隔开第二预定距离，优选地与第一方向成直角。 每个浮置栅极形成在第一和第二隔离晶体之间以及重掺杂杂质区之间。 控制栅极线形成在第一和第二隔离区域之间，并且在与第一和第二隔离区域相同的方向上在浮动栅极上形成。 擦除栅极线形成为具有比浮动栅极窄的宽度，并且形成在浮动栅极上，优选地与控制栅极线成直角。