公开(公告)号：US20250111121A1

公开(公告)日：2025-04-03

申请号：US18478469

申请日：2023-09-29

Applicant: Advanced Micro Devices, Inc.

Inventor： Ashish Jain ,  Lakshminarayana Pappu

IPC: G06F30/373

Abstract: An apparatus and method for efficiently managing performance and power consumption among replicated functional blocks of an integrated circuit despite different circuit behavior amongst the functional blocks due to manufacturing variations. An integrated circuit includes multiple replicated functional blocks, each being a semiconductor die with a corresponding communication fabric for routing packets. A second functional block placed between a first functional block and a third functional block routes packets to destinations from at least the first and the third functional blocks, and provides higher performance than the first and the third functional blocks due to semiconductor manufacturing variations. A power manager assigns a single power supply voltage to the replicated functional blocks, and assigns a target clock frequency to the first and the third functional blocks. The power manager assigns another clock frequency greater than the target clock frequency to the second functional block.

公开(公告)号：US20250110861A1

公开(公告)日：2025-04-03

申请号：US18374815

申请日：2023-09-29

Applicant: Advanced Micro Devices, Inc.

Inventor： Moumita Dey ,  Varun Agrawal

IPC: G06F12/02

Abstract: In accordance with the described techniques for data compression using reconfigurable hardware based on data redundancy patterns, a computing device includes a memory, processing-in-memory units, a host processing unit, and a compression unit having reconfigurable logic for performing multiple compression algorithms. The host processing unit issues processing-in-memory requests instructing the processing-in-memory units to scan a block of the memory for one or more data redundancy patterns, and to identify a compression algorithm of the multiple compression algorithms based on the one or more data redundancy patterns. Further, the host processing unit issues a memory request to access a memory address in the block of the memory. The memory request causes data of the memory address to be communicated from the block of the memory to the compression unit to be compressed using the compression algorithm.

公开(公告)号：US20250110792A1

公开(公告)日：2025-04-03

申请号：US18374263

申请日：2023-09-28

Applicant: Advanced Micro Devices, Inc.

Inventor： Stephen Alexander Zekany ,  Anthony Thomas Gutierrez

IPC: G06F9/50

Abstract: In accordance with the described techniques, a host processor receives a task graph including tasks and indicating dependencies between the task graph. The host processor formats the task graph, in part, by sorting the tasks of the task graph in an order based on the dependencies between the tasks. Further, the host processor submits the formatted task graph to a scalable input/output virtualization (SIOV) device, which directs the SIOV device to process the tasks of the task graph based on the order.

公开(公告)号：US12266139B2

公开(公告)日：2025-04-01

申请号：US17551097

申请日：2021-12-14

Applicant: Advanced Micro Devices, Inc.

Inventor： Christopher J. Brennan ,  Pazhani Pillai

IPC: G06T9/00 ,  G06T15/00

Abstract: A method and apparatus for integrating data compression in a computer system includes receiving first data at a first system level. Based upon a number of planes of the first data being less than or equal to a threshold, the data is compressed with a first data compression scheme, and transferred to a second system level for processing. Based upon the number of planes of the first data exceeding the threshold, the first data is transferred uncompressed to the second system level for processing. Based upon the received data at the second system level being compressed with the first compression scheme, the data is transferred to a third system level, and based upon the received data at the second system level being uncompressed with the first compression scheme, compressing the data with a second compression scheme, and transferring the compressed data to the third system level.

公开(公告)号：US12265735B2

公开(公告)日：2025-04-01

申请号：US17845263

申请日：2022-06-21

Applicant: Advanced Micro Devices, Inc.

Inventor： Shaizeen Aga ,  Nuwan Jayasena

IPC: G06F3/06

Abstract: An approach is provided for processing near-memory processing commands, e.g., PIM commands, using PIM register definition data that defines multiple combinations of source and/or destination registers to be used to process PIM commands. A particular combination of source and/or destination registers to be used to process a PIM command is specified by the PIM command or determined by a near-memory processing element processing the PIM command. According to another implementation, the PIM register definition data specifies an initial combination of source and/or destination registers and one or more update functions for each PIM command. A near-memory processing element processes a PIM command using the initial combination of source and/or destination registers and uses the one or more update functions to update the combination of source and/or destination registers to be used the next time the PIM command is processed.

公开(公告)号：US20250106508A1

公开(公告)日：2025-03-27

申请号：US18476011

申请日：2023-09-27

Applicant: Advanced Micro Devices, Inc.

Inventor： Po-Min Wang

IPC: H04N23/68 ,  H04N5/265

Abstract: A technique for generating video is provided. The technique includes obtaining a plurality of source frames with a wide-angle camera and a narrow-angle camera; identifying a plurality of central portions and a plurality of peripheral portions of the plurality of source frames based on image stabilization; and combining the plurality of central portions and the plurality of peripheral portions to generate a plurality of resulting frames of an output video.

公开(公告)号：US20250103650A1

公开(公告)日：2025-03-27

申请号：US18371010

申请日：2023-09-21

Applicant: Advanced Micro Devices, Inc.

Inventor： Kishore Punniyamurthy ,  Jagadish B. Kotra

IPC: G06F16/901

Abstract: Graph analytics system are described. In accordance with the described techniques, a graph having vertices that include a first vertex and a second vertex that are associated with access control metadata are received. An updated graph is output based on a merging of the first vertex and the second vertex into a merged vertex of a group of vertices based on the first vertex and the second vertex being associated with access control metadata common to the first vertex and the second vertex and based on a reordering technique. A single copy of the access control metadata is stored for the first vertex and the second vertex.

公开(公告)号：US20250103297A1

公开(公告)日：2025-03-27

申请号：US18372593

申请日：2023-09-25

Applicant: Advanced Micro Devices, Inc.

Inventor： Changhoon YEO ,  Tun-Fen WANG ,  Ajay K. DAWRA

IPC: G06F7/58

Abstract: Techniques for detecting a digital pseudo-random sequence (PRS) using fast locking, including repeatedly computing a first PRS seed based on an ADC output, generating a PRS sequence based on the first seed, computing a second PRS seed based on the sequence, and comparing the sequence to the ADC output (comparison results may be provided as a bool signal), until the sequence matches the ADC output. Thereafter, the technique may include re-computing the sequence based on the second seed, re-computing the second seed based on the re-computed sequence and comparing the re-computed sequence to the ADC output. The technique may further include setting a lock when a threshold number of sequences computed from the second seed match the ADC output, and reverting to computing the sequence based on the first seed if a sequence computed from the second seed does not match the ADC output and the lock is not set.

公开(公告)号：US20250098184A1

公开(公告)日：2025-03-20

申请号：US18470582

申请日：2023-09-20

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Arsalan Alam ,  Anadi Srivastava ,  Rajen Singh Sidhu ,  Alexander Helmut Pfeiffenberger ,  Liwei Wang

IPC: H01L23/522 ,  H01L23/64

Abstract: A method for increasing capacitance density within an integrated passive device can include forming a first trench capacitor within a substrate, forming a second trench capacitor within an insulating layer overlying the substrate, and connecting the first and second trench capacitors through connection vias that extend through the insulating layer to form an integrated passive device (IPD) capacitor. A high capacitance density device can include a stacked and co-integrated architecture of two or more tiers of trench capacitors.

公开(公告)号：US20250096136A1

公开(公告)日：2025-03-20

申请号：US18471114

申请日：2023-09-20

Applicant: Advanced Micro Devices, Inc. ,  Xilinx, Inc.

Inventor： Divya Madapusi Srinivas Prasad ,  Gabriel H. Loh ,  Richard Schultz ,  Jeffrey Richard Rearick ,  Shidhartha Das ,  Suresh Ramalingam

IPC: H01L23/528 ,  H01L23/48

Abstract: A disclosed semiconductor device includes (1) a silicon stack comprising a front-side Back-End-of-Line (BEOL) stack and a back side BEOL stack, the front-side BEOL stack comprising a plurality of signal routes and the back-side BEOL stack comprising a plurality of power delivery routes, and (2) a plurality of auxiliary power paths formed within the front-side BEOL stack and electrically coupled to the plurality of power delivery routes of the back-side BEOL stack via a plurality of programmable switches, the plurality of power delivery routes, the plurality of programmable switches, and the plurality of auxiliary power paths forming a programmable power delivery network (PDN). Various other apparatuses, systems, and methods of operation are also disclosed.