公开(公告)号：US20250141266A1

公开(公告)日：2025-05-01

申请号：US18824137

申请日：2024-09-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Bumjin PARK ,  Jedok KIM ,  Seho PARK ,  Sungku YEO ,  Hana CHOE

IPC: H02J50/10 ,  H02J7/00

Abstract: An electronic device (e.g., a power supply device or a power receiving device) includes a housing including a first side of the electronic device and a second side opposite to the first side, a wireless charging coil disposed in the housing, and a magnet structure disposed in the housing to surround the coil and including a plurality of magnet pieces including a first magnet piece and a second magnet piece. The first magnet piece includes a first outer magnetized area having an N pole facing the first side, a first inner magnetized area disposed closer to the coil than the first outer magnetized area and having an S pole facing the first side, and a first non-magnetized area disposed between the first outer magnetized area and the first inner magnetized area. The second magnet piece includes a second outer magnetized area having an N pole facing the first side, a second inner magnetized area disposed closer to the coil than the second outer magnetized area and having an S pole facing the first side, and a second non-magnetized area disposed between the second outer magnetized area and the second inner magnetized area. The first magnet piece has a first magnetic force and the second magnet piece has a second magnetic force different from the first magnetic force.

公开(公告)号：US20250140720A1

公开(公告)日：2025-05-01

申请号：US18763547

申请日：2024-07-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： DAWOON JUNG

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/48 ,  H01L25/065

Abstract: A semiconductor package includes a first semiconductor chip, a chip structure on the first semiconductor chip, and a bonding structure between the first semiconductor chip and the chip structure, where the bonding structure includes a first conductive pad on an upper surface of the first semiconductor chip, a second conductive pad on a lower surface of the chip structure, a protective metal layer between the first conductive pad and the second conductive pad, and an intermetallic compound in the protective metal layer, where the protective metal layer covers a surface of the first conductive pad and a surface of the second conductive pad, where the semiconductor package further includes a first interface between the first semiconductor chip and the chip structure and a second interface between the protective metal layer and the second conductive pad.

公开(公告)号：US20250140705A1

公开(公告)日：2025-05-01

申请号：US18749750

申请日：2024-06-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyuhyeon Choi

IPC: H01L23/538 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L25/18 ,  H10B80/00

Abstract: A semiconductor package includes a package substrate, a first semiconductor chip on the package substrate and including a plurality of first through vias, a second semiconductor chip spaced apart from the first semiconductor chip in a lateral direction parallel to an upper surface of the package substrate and including a plurality of second through vias, a third semiconductor chip on the first semiconductor chip, an interposer between the third semiconductor chip and the first semiconductor chip and electrically connecting the first semiconductor chip to the third semiconductor chip, a molding layer between the package substrate and the interposer and on the first semiconductor chip and the second semiconductor chip, a first solder ball between the first semiconductor chip and the interposer, and a second solder ball between the second semiconductor chip and the interposer.

公开(公告)号：US20250140678A1

公开(公告)日：2025-05-01

申请号：US18783847

申请日：2024-07-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jihyun LEE ,  Insik HAN

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/00 ,  H01L23/31

Abstract: A substrate includes a base substrate comprising a center region and a corner region in a plan view. The base substrate comprises wiring patterns and an insulating layer. First conductive pads are on an upper surface of the center region of the base substrate. Second conductive pads are on an upper surface of the corner region of the base substrate. Each of the first conductive pads has a circular or oval shape in the plan view. Each of the second conductive pads has a polygonal shape in the plan view.

公开(公告)号：US20250140619A1

公开(公告)日：2025-05-01

申请号：US18927331

申请日：2024-10-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Bongsoo KIM ,  Chobi KIM ,  Pyunghwa HAN

IPC: H01L23/14 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498

Abstract: A semiconductor package includes: a first interconnection structure; an expanded layer arranged on the first interconnection structure, the expanded layer comprising a plurality of expanded base layers; a semiconductor chip arranged in a mounting space and electrically connected to the first interconnection structure; a filling insulating layer configured to fill the mounting space; and a second interconnection structure arranged on the expanded layer and the filling insulating layer, the second interconnection structure electrically connected to the first interconnection structure through a plurality of via structures, in which a surface of a lowermost expanded base layer among the plurality of expanded base layers is positioned at a higher vertical level than a surface of the filling insulating layer, and a sink space is confined by the expanded layer and the filling insulating layer under a surface of the lowermost expanded base layer among the plurality of expanded base layers.

公开(公告)号：US20250140595A1

公开(公告)日：2025-05-01

申请号：US18904870

申请日：2024-10-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yeontae Kim ,  Yihwan Kim ,  Woohyung Kim ,  Sunwoo Bang ,  Kwanghyun Yang

IPC: H01L21/687 ,  H01J37/32 ,  H01L21/67

Abstract: An apparatus for processing a substrate is provided and includes: a chamber including an internal space; a shower head in the internal space of the chamber; a heater below the shower head; lift pins configured to lift the substrate, relative to the heater, while the substrate is on the heater; a rotation shaft connected to the heater; a rotation driving actuator connected to the rotation shaft and configured to rotate the heater by rotating the rotation shaft; a first lifting driving actuator configured to lift the heater; a lifting member configured to lift the lift pins; and a second lifting driving actuator connected to the lifting member and configured to lift the lift pins, relative to the heater, by lifting the lifting member.

公开(公告)号：US20250140588A1

公开(公告)日：2025-05-01

申请号：US18790371

申请日：2024-07-31

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ilyoung HAN ,  Sumin KIM ,  Minwoo RHEE ,  Hyunjin LEE ,  Kyeongbin LIM

IPC: H01L21/677 ,  H01L21/67 ,  H01L21/68

Abstract: A wafer on which a hydrophilic pattern is applied is provided to a die seat on which a first magnetic pattern is formed and a hydrophobic pattern is applied around the hydrophilic pattern. Liquid is dispensed to the die seat. A first die on which a second magnetic pattern is formed is seated on the wafer and the first die is first-aligned using capillary force of the liquid. Liquid is dispensed onto an upper surface of the first die. A second die is seated on the upper surface of the first die and the second die is first-aligned with capillary force of the liquid on the upper surface of the first die. A magnetic field is generated in the first magnetic pattern and the second magnetic pattern and the first magnetic pattern and the second magnetic pattern are secondly-aligned using magnetic force.

公开(公告)号：US20250140316A1

公开(公告)日：2025-05-01

申请号：US18909041

申请日：2024-10-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kwangsoo Kim

IPC: G11C16/04 ,  H01L25/065 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/41 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40 ,  H10B80/00

Abstract: A semiconductor device includes a peripheral circuit structure and a cell structure stacked on the peripheral circuit structure, the cell structure including gate electrodes spaced apart from each other in a vertical direction, a channel structure arranged within a channel hole extending in the vertical direction by passing through the gate electrodes, including a channel layer and a back gate electrode spaced apart from the channel layer, and including a first end portion arranged adjacent to the peripheral circuit structure and a second end portion opposite to the first end portion, a common source layer connected to the channel layer at the second end portion of the channel structure, an upper insulating layer on the common source layer, and a back gate contact arranged within a first backside contact hole passing through the upper insulating layer and the common source layer and connected to the back gate electrode.

公开(公告)号：US20250139945A1

公开(公告)日：2025-05-01

申请号：US18663547

申请日：2024-05-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyuhyun SHIM ,  Seongeun KIM ,  Seohyung LEE

IPC: G06V10/774 ,  G06T5/50 ,  G06T5/77 ,  G06V10/26 ,  G06V10/764 ,  G06V10/82

Abstract: A method and apparatus with data augmentation are disclosed. The a method includes: based on information about objects included in target data, extracting a region for object synthesis from a point cloud of the target data; determining a target object based on location information about the extracted region; based on a point cloud of the target object and the point cloud of the target data, synthesizing the point cloud of the target object with the extracted region to generate a synthetic point cloud; and generating a synthetic image by synthesizing an image of the target object with an image of the target data based on the location information about the extracted region and the point cloud of the target object, wherein the synthetic point cloud and the synthetic image form an augmented training item.

公开(公告)号：US20250139762A1

公开(公告)日：2025-05-01

申请号：US18890365

申请日：2024-09-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyunchul KIM ,  Daewoong Choi ,  Ohchel Kwon ,  Hyunmo Kang ,  Taecheon Kim ,  Jinhong Park ,  Wooseok Choe

IPC: G06T7/00 ,  H01L21/66

Abstract: A wafer inspection method includes: obtaining an inspection image by capturing an image of a wafer and an identification tag; obtaining an inspection profile by quantifying the identification tag in the inspection image; and performing a surface inspection of the wafer based on the obtained inspection profile.