DOWNLINK SLOT STRUCTURE, CHANNEL PLACEMENT, AND PROCESSING TIMELINE OPTIONS

    公开(公告)号:US20170353947A1

    公开(公告)日:2017-12-07

    申请号:US15613014

    申请日:2017-06-02

    Abstract: Aspects of the disclosure provide a slot structure (e.g., the arrangement of channels and pilot signals within a slot) that can relax the processing timeline for a wireless communication device. For example, in the first or initial symbol of a slot, control information may be frequency division multiplexed (FDM) with a demodulation reference signal (DMRS) or with user data. In some cases, delayed-processing data may be sampled, and the samples may be buffered at the receiving device, for processing later, after control information needed to process the data has been received and processed. Further aspects provide for payload pre-tapering. That is, when a device delays the processing of data bits, this can cause a processing bottleneck after that buffering delay. By virtue of various pre-tapering techniques described herein, the processing load needed to process the delayed-processing data can be reduced. Other aspects, embodiments, and features are also claimed and described.

    BACK-TO-BACK REFERENCE SIGNALS
    197.
    发明申请

    公开(公告)号:US20170141896A1

    公开(公告)日:2017-05-18

    申请号:US15231591

    申请日:2016-08-08

    Abstract: Methods, systems, and devices for wireless communication are described. A base station may select a two sets of reference signal resource elements (REs) for a symbol period, where each RE of the first set is contiguous to an RE of the second set. The base station may also identify resource element groups (REGs) for control signaling, where each REG covers one or more resource blocks (RBs). The base station may then perform interference cancellation, which may be based on an interference covariance matrix for each of the REGs. In some cases, the base station may coordinate with neighboring base stations (directly or through the core network) to ensure that the selected REGs do not partially overlap with reference signal transmissions or REGs of neighboring base stations.

    TIME DIVISION DUPLEX (TDD) SUBFRAME STRUCTURE SUPPORTING SINGLE AND MULTIPLE INTERLACE MODES
    200.
    发明申请
    TIME DIVISION DUPLEX (TDD) SUBFRAME STRUCTURE SUPPORTING SINGLE AND MULTIPLE INTERLACE MODES 有权
    时分双工(TDD)子帧结构支持单个和多个接口模式

    公开(公告)号:US20170026992A1

    公开(公告)日:2017-01-26

    申请号:US15051949

    申请日:2016-02-24

    Abstract: Aspects of the present disclosure provide a time division duplex (TDD) subframe structure that supports both single and multiple interlace modes of operation. In a single interlace mode, control information, data information corresponding to the control information and acknowledgement information corresponding to the data information are included in a single subframe. In a multiple interlace mode, at least one of the control information, the data information corresponding to the control information or the acknowledgement information corresponding to the data information is included in a different subframe. Both single and multiple interlace modes can be multiplexed together within the TDD subframe structure.

    Abstract translation: 本公开的方面提供了支持单个和多个隔行操作模式的时分双工(TDD)子帧结构。 在单个交错模式中,控制信息,对应于控制信息的数据信息和对应于数据信息的确认信息被包括在单个子帧中。 在多交错模式中,控制信息,对应于控制信息的数据信息或对应于数据信息的确认信息中的至少一个被包括在不同的子帧中。 单个和多个隔行扫描模式可以在TDD子帧结构内复用在一起。

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