公开(公告)号：US11003827B1

公开(公告)日：2021-05-11

申请号：US16796855

申请日：2020-02-20

Applicant: XILINX, INC.

Inventor： Paul D. Kundarewich ,  Grigor S. Gasparyan ,  Mehrdad Eslami Dehkordi ,  Guenter Stenz ,  Zhaoxuan Shen ,  Amish Pandya

IPC: G06F30/392 ,  G06F111/04

Abstract: Examples described herein provide a non-transitory computer-readable medium storing instructions, which when executed by one or more processors, cause the one or more processors to perform operations. The operations include: generating, using the one or more processors, a plurality of child processes according to a number of programmable dies of the multi-die device, each of the plurality of child processes corresponding to a respective programmable die of the multi-die device, wherein the plurality of child processes execute on different processors; partitioning a design for the multi-die device into a plurality of portions, each of the portions to be used to configure one of the programmable dies of the multi-die device; transmitting the plurality of portions of the design to the plurality of child processes for placement; and receiving placements from the plurality of child processes.

公开(公告)号：US10783295B1

公开(公告)日：2020-09-22

申请号：US16399493

申请日：2019-04-30

Applicant: Xilinx, Inc.

Inventor： Xiao Dong ,  Grigor S. Gasparyan ,  Abhishek Joshi

IPC: G06F30/00 ,  G06F30/327 ,  G06F30/34

Abstract: An example method for compiling includes, by a processor-based system: obtaining a netlist of an application, the netlist containing program nodes and respective edges between the program nodes, the application to be implemented on a device comprising an array of data processing engines; partitioning the netlist into a plurality of partitions; for each of the plurality of partitions: generating a global mapping of the program nodes based on a representation of the array of data processing engines and using an integer linear programming (ILP) algorithm; generating a detailed mapping of the program nodes based on the global mapping; and translating the detailed mapping for each of the plurality of partitions to a file.

公开(公告)号：US10126361B1

公开(公告)日：2018-11-13

申请号：US15351085

申请日：2016-11-14

Applicant: Xilinx, Inc.

Inventor： Xiaojian Yang ,  Maogang Wang ,  Grigor S. Gasparyan ,  Raoul Badaoui

IPC: G06F17/50 ,  G01R31/317 ,  G01R31/3177

Abstract: Processing a circuit design that specifies application logic and debugging logic includes partitioning the circuit design. Each partition includes a part of the application logic and a part of the debugging logic, each partition is specified for implementation on a respective IC die, and the circuit design specifies connections between a part of the application logic in one partition and a part of the debugging logic in another partition. The connections between the part of the application logic in the one partition and the part of the debugging logic in the other partition are changed to connections from the part of the application logic in the one partition to a part of the debugging logic in the one partition. The part of the application logic and the part of the debugging logic of each partition are placed and routed on the respective IC die.

公开(公告)号：US10108769B1

公开(公告)日：2018-10-23

申请号：US15295911

申请日：2016-10-17

Applicant: Xilinx, Inc.

Inventor： Yau-Tsun S. Li ,  Grigor S. Gasparyan

IPC: G06F17/50

Abstract: Designing circuits can include, within a circuit design, detecting, using a processor, a high fan-out net having loads with a same timing requirement, wherein the circuit design is technology specific for a target integrated circuit (IC), determining, using the processor, a region having a predetermined shape and an area sized to fit loads of the high fan-out net within the region on the target IC, and determining, using the processor, a delay of the high fan-out net based upon a distance from a center of the region to an edge of the region. Designing circuits can also include assigning, using the processor, the delay to the high fan-out net.