公开(公告)号：US20210151353A1

公开(公告)日：2021-05-20

申请号：US17140794

申请日：2021-01-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsun-Chung Kuang ,  Yen-Chang Chu ,  Cheng-Tai Hsiao ,  Ping-Yin Liu ,  Lan-Lin Chao ,  Yeur-Luen Tu ,  Chia-Shiung Tsai ,  Xiaomeng Chen

IPC: H01L21/768 ,  H01L23/00 ,  H01L23/31 ,  H01L25/04 ,  H01L25/075 ,  H01L23/538 ,  H01L25/065 ,  H01L23/29 ,  H01L25/00

Abstract: An integrated circuit structure includes a package component, which further includes a non-porous dielectric layer having a first porosity, and a porous dielectric layer over and contacting the non-porous dielectric layer, wherein the porous dielectric layer has a second porosity higher than the first porosity. A bond pad penetrates through the non-porous dielectric layer and the porous dielectric layer. A dielectric barrier layer is overlying, and in contact with, the porous dielectric layer. The bond pad is exposed through the dielectric barrier layer. The dielectric barrier layer has a planar top surface. The bond pad has a planar top surface higher than a bottom surface of the dielectric barrier layer.

公开(公告)号：US10163651B1

公开(公告)日：2018-12-25

申请号：US15883748

申请日：2018-01-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sheng-Chau Chen ,  Cheng-Tai Hsiao ,  Cheng-Yuan Tsai ,  Hsun-Chung Kuang ,  Yao-Wen Chang

IPC: H01L45/00 ,  H01L21/311 ,  H01L21/3105 ,  H01L43/02 ,  H01L23/528 ,  H01L43/08

Abstract: A memory cell with an etch stop layer is provided. The memory cell comprises a bottom electrode disposed over a substrate. A switching dielectric is disposed over the bottom electrode and having a variable resistance. A top electrode is disposed over the switching dielectric. A sidewall spacer layer extends upwardly along sidewalls of the bottom electrode, the switching dielectric, and the top electrode. A lower etch stop layer is disposed over the lower dielectric layer and lining an outer sidewall of the sidewall spacer layer. The lower etch stop layer is made of a material different from the sidewall spacer layer and protects the top electrode from damaging during manufacturing processes. A method for manufacturing the memory cell is also provided.

公开(公告)号：US11367623B2

公开(公告)日：2022-06-21

申请号：US17070461

申请日：2020-10-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sheng-Chau Chen ,  Cheng-Tai Hsiao ,  Cheng-Yuan Tsai ,  Hsun-Chung Kuang ,  Yao-Wen Chang

IPC: H01L45/00 ,  H01L21/311 ,  H01L21/3105 ,  H01L43/02 ,  H01L23/528 ,  H01L43/08 ,  H01L43/12

Abstract: A method of forming a memory device is provided. In some embodiments, a memory cell is formed over a substrate, and a sidewall spacer layer is formed along the memory cell. A lower etch stop layer is formed on the sidewall spacer layer, and an upper dielectric layer is formed on the lower etch stop layer. A first etching process is performed to etch back the upper dielectric layer using the lower etch stop layer as an etch endpoint.

公开(公告)号：US11183627B2

公开(公告)日：2021-11-23

申请号：US16732385

申请日：2020-01-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sheng-Chau Chen ,  Cheng-Tai Hsiao ,  Cheng-Yuan Tsai ,  Hsun-Chung Kuang

IPC: H01L27/22 ,  H01L43/02 ,  H01L43/12

Abstract: Some embodiments relate to a memory device. The memory device includes a memory cell overlying a substrate, the memory cell includes a data storage structure disposed between a lower electrode and an upper electrode. An upper interconnect wire overlying the upper electrode. A first inter-level dielectric (ILD) layer surrounding the memory cell and the upper interconnect wire. A second ILD layer overlying the first ILD layer and surrounding the upper interconnect wire. A sidewall spacer laterally surrounding the memory cell. The sidewall spacer has a first sidewall abutting the first ILD layer and a second sidewall abutting the second ILD layer.

公开(公告)号：US10727077B2

公开(公告)日：2020-07-28

申请号：US16220200

申请日：2018-12-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sheng-Chau Chen ,  Cheng-Tai Hsiao ,  Cheng-Yuan Tsai ,  Hsun-Chung Kuang ,  Yao-Wen Chang

IPC: H01L43/08 ,  H01L21/311 ,  H01L45/00 ,  H01L21/3105 ,  H01L43/02 ,  H01L23/528 ,  H01L43/12

Abstract: A memory cell with an etch stop layer is provided. The memory cell comprises a bottom electrode disposed over a substrate. A switching dielectric is disposed over the bottom electrode and having a variable resistance. A top electrode is disposed over the switching dielectric. A sidewall spacer layer extends upwardly along sidewalls of the bottom electrode, the switching dielectric, and the top electrode. A lower etch stop layer is disposed over the lower dielectric layer and lining an outer sidewall of the sidewall spacer layer. The lower etch stop layer is made of a material different from the sidewall spacer layer and protects the top electrode from damaging during manufacturing processes.

公开(公告)号：US20190157099A1

公开(公告)日：2019-05-23

申请号：US16220200

申请日：2018-12-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sheng-Chau Chen ,  Cheng-Tai Hsiao ,  Cheng-Yuan Tsai ,  Hsun-Chung Kuang ,  Yao-Wen Chang

IPC: H01L21/311 ,  H01L23/528 ,  H01L43/08 ,  H01L45/00 ,  H01L21/3105 ,  H01L43/02

Abstract: A memory cell with an etch stop layer is provided. The memory cell comprises a bottom electrode disposed over a substrate. A switching dielectric is disposed over the bottom electrode and having a variable resistance. A top electrode is disposed over the switching dielectric. A sidewall spacer layer extends upwardly along sidewalls of the bottom electrode, the switching dielectric, and the top electrode. A lower etch stop layer is disposed over the lower dielectric layer and lining an outer sidewall of the sidewall spacer layer. The lower etch stop layer is made of a material different from the sidewall spacer layer and protects the top electrode from damaging during manufacturing processes.