RECEIVER ARCHITECTURE DEMODULATING 4N-QAM DIRECTLY IN ANALOG DOMAIN WITHOUT ANALOG-TO-DIGITAL CONVERTER (ADC)

    公开(公告)号:US20250168051A1

    公开(公告)日:2025-05-22

    申请号:US19026969

    申请日:2025-01-17

    Abstract: Disclosed are example embodiments of a receiver. The receiver including a front-end amplification and filtering block configured to amplify a received signal and filter out a potential jammer signal from a communication channel. The receiver also including a quadrature mixer, coupled to the front-end amplification and filtering block, and configured to down-convert the amplified and filtered signal to baseband to generate a quadrature LO signal. Additionally, the receiver including a carrier synchronization loop configured to synchronize the quadrature LO signal and carrier phase of the received signal. The receiver also including a demodulator coupled to the quadrature mixer and the carrier synchronization loop.

    HIGH RESOLUTION ELECTROENCEPHALOGRAPH SIGNAL ACQUISITION SYSTEM

    公开(公告)号:US20230355156A1

    公开(公告)日:2023-11-09

    申请号:US18245120

    申请日:2021-12-09

    CPC classification number: A61B5/31 A61B5/369

    Abstract: This invention discloses a non-invasive electroencephalography (BEG) signal recorder and a multiband active electrode (MAE) EEG cap array. A narrow-band amplification method is disclosed that divides the desired bandwidth of the input brain signal to smaller bands, each recorded using a separate amplification path. A novel twisted differential feedback topology is disclosed for both amplifiers and active filters having ultra-high input impedance. A one-wire EEG cap array of tightly connected MAEs is disclosed that improves the flexibility and portability of the EEG cap by reducing the number of wires between the EEG cap and the host processor. Due to having MAEs embedded inside electrodes, the output signals of electrodes are digital information. The tightly connected network of MAEs enables the reference electrode to be chosen dynamically. Moreover, the voltage of the reference node is adjusted using a correction feedback loop before each recording step.

    Millimeter-wave scalable PLL-coupled array for phased-array applications

    公开(公告)号:US11749890B2

    公开(公告)日:2023-09-05

    申请号:US18151697

    申请日:2023-01-09

    CPC classification number: H01Q3/36 H03L7/0802

    Abstract: Techniques, systems and architectures for generating desired phase shifts in a phased array to control the directions of radiation in a wide range of angles are disclosed. Particularly, phased array architectures based on novel PLL-coupled phase shifting techniques for implementation in millimeter-wave (mm-wave) and sub-terahertz (sub-THz) operations range are described. In one aspect, a phased array including an array of unit cells is disclosed. In some embodiments, each unit cell in the array of unit cells includes a dual-nested PLL that is configured to effectuate phase locking and frequency locking to a reference signal from an adjacent unit cell. Moreover, each PLL includes control circuitry that can generate a wide range of phase shifts between adjacent unit cells to facilitate phased-array operations. Note that using the dual-nested PLL to generate a desired phase shift between adjacent radiating elements eliminates the use of conventional lossy phase shifters in the phased array.

    MILLIMETER-WAVE SCALABLE PLL-COUPLED ARRAY FOR PHASED-ARRAY APPLICATIONS

    公开(公告)号:US20230163461A1

    公开(公告)日:2023-05-25

    申请号:US18151697

    申请日:2023-01-09

    CPC classification number: H01Q3/36 H03L7/0802

    Abstract: Techniques, systems and architectures for generating desired phase shifts in a phased array to control the directions of radiation in a wide range of angles are disclosed. Particularly, phased array architectures based on novel PLL-coupled phase shifting techniques for implementation in millimeter-wave (mm-wave) and sub-terahertz (sub-THz) operations range are described. In one aspect, a phased array including an array of unit cells is disclosed. In some embodiments, each unit cell in the array of unit cells includes a dual-nested PLL that is configured to effectuate phase locking and frequency locking to a reference signal from an adjacent unit cell. Moreover, each PLL includes control circuitry that can generate a wide range of phase shifts between adjacent unit cells to facilitate phased-array operations. Note that using the dual-nested PLL to generate a desired phase shift between adjacent radiating elements eliminates the use of conventional lossy phase shifters in the phased array.

    INTEGRATED WIDEBAND STEPPED-CHIRP RADAR SENSOR

    公开(公告)号:US20220404483A1

    公开(公告)日:2022-12-22

    申请号:US17856005

    申请日:2022-07-01

    Abstract: The disclosed FMCW radar system is configured to achieve a wide synthetic bandwidth of operation and a high range resolution. The disclosed FMCW radar system includes a receiver that combines the intermediate frequency (IF) components of multiple narrowband receivers to achieve the millimeter-scale range resolution. The disclosed FMCW radar system can be easily scaled, which enables it to be deployed in large arrays of antennas in order to attain high angular resolution. Additionally, the operation frequency of the disclosed FMCW radar system enables millimeter level cross-range resolution. In this manner, accurate estimation of the location and/or velocity of the objects within the local-sensing range (and potentially beyond) can be achieved.

    Multi-channel code-division multiplexing in front-end integrated circuits
    19.
    发明授权
    Multi-channel code-division multiplexing in front-end integrated circuits 有权
    前端集成电路中的多通道码分复用

    公开(公告)号:US09001848B2

    公开(公告)日:2015-04-07

    申请号:US13686803

    申请日:2012-11-27

    CPC classification number: H04J13/10 H04B1/707 H04B2201/70707

    Abstract: A code-division multiplexing (CDM) system utilized in multi-channel (MC) front-end integrated circuits to significantly reduce the power consumption of such systems. The CDM system extends data compression advantages to uncorrelated and weakly correlated MC signals through the introduction of a new Multi-Channel Signal Binning and Multiplexing (MCSBM) method and architecture. The method achieves significant reductions in power consumption in comparison to a conventional time-division multiplexing quantizer, while adding only a modest amount of overhead and complexity. Systems and methods permit architects to fabricate MC integrated circuits with ultra low power consumption and small chip area. Another embodiment relates to the system's compressor organizing samples of the input signal in such a way that the downstream analog-to-digital converter quantizes the higher variance samples with a higher resolution compared to the resolution it uses to quantize other samples with lower variance.

    Abstract translation: 在多通道(MC)前端集成电路中使用的码分多路复用(CDM)系统可显着降低这种系统的功耗。 CDM系统通过引入新的多信道信号分组和复用(MCSBM)方法和架构,将数据压缩优势扩展到不相关和弱相关的MC信号。 与传统的时分复用量化器相比,该方法实现了功耗的显着降低,同时仅增加了适量的开销和复杂度。 系统和方法允许建筑师制造具有超低功耗和小芯片面积的MC集成电路。 另一实施例涉及系统的压缩机组合输入信号的样本,使得下游模数转换器与其用于量化具有较低方差的其他样本的分辨率相比,以更高的分辨率量化较高方差样本。

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