公开(公告)号：US20200076419A1

公开(公告)日：2020-03-05

申请号：US16360914

申请日：2019-03-21

Applicant: Texas Instruments Incorporated

Inventor： Mayank Garg

IPC: H03K17/16 ,  H01L27/06 ,  H01L27/02 ,  H03K17/082

Abstract: Methods, apparatus, systems and articles of manufacture are disclosed that provide an apparatus comprising: a first transistor including a first gate, a first current terminal, and a second current terminal; a second transistor including a second gate, a third current terminal, and a fourth current terminal; the first current terminal coupled to the third current terminal; the first gate coupled to the second gate and the second current terminal; a third transistor including a third gate, a fifth current terminal, and a sixth current terminal, the fifth current terminal coupled to the second current terminal, third gate coupled to a voltage reference node; and a fourth transistor including a fourth gate, a seventh current terminal and an eighth current terminal, the seventh current terminal coupled to the sixth current terminal, the fourth gate coupled to the seventh current terminal and the eighth current terminal coupled to the fourth current terminal.

公开(公告)号：US20240396554A1

公开(公告)日：2024-11-28

申请号：US18792708

申请日：2024-08-02

Applicant: Texas Instruments Incorporated

Inventor： Win Naing Maung ,  Bharath Kumar Singareddy ,  Soumi Paul ,  Mayank Garg ,  Suzanne Mary Vining

IPC: H03K19/0185 ,  G06F13/42 ,  H04B3/36 ,  H04L7/00 ,  H04L25/02

Abstract: A circuit includes signal conditioner circuitry, level shifter circuitry, and state detector and controller circuitry coupled between the signal conditioner circuitry and the level shifter circuitry. The state detector and controller circuitry includes receiver circuitry and a finite state machine coupled to the receiver circuitry. The finite state machine is configured to detect a first data rate from signals, control operation of the signal conditioner circuitry responsive to detecting the first data rate, and control operation of the level shifter circuitry during a second data rate.

公开(公告)号：US12088293B2

公开(公告)日：2024-09-10

申请号：US17700045

申请日：2022-03-21

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Win Naing Maung ,  Bharath Kumar Singareddy ,  Soumi Paul ,  Mayank Garg ,  Suzanne Mary Vining

IPC: H03K19/0185 ,  G06F13/42 ,  H04B3/36 ,  H04L7/00 ,  H04L25/02

CPC classification number: H03K19/018521 ,  G06F13/4282 ,  H04B3/36 ,  H04L7/0041 ,  H04L25/0272

Abstract: A circuit includes signal conditioner circuitry, level shifter circuitry, and state detector and controller circuitry coupled between the signal conditioner circuitry and the level shifter circuitry. The state detector and controller circuitry includes receiver circuitry and a finite state machine coupled to the receiver circuitry. The finite state machine is configured to detect a first data rate from signals, control operation of the signal conditioner circuitry responsive to detecting the first data rate, and control operation of the level shifter circuitry during a second data rate.

公开(公告)号：US20230155628A1

公开(公告)日：2023-05-18

申请号：US18100131

申请日：2023-01-23

Applicant: Texas Instruments Incorporated

Inventor： Srijan Rastogi ,  Mayank Garg ,  Anant Shankar Kamath

IPC: H04B3/36 ,  H03F3/45

CPC classification number: H04B3/36 ,  H03F3/45179

Abstract: Universal Serial Bus (USB) repeater circuits and methods of operating the same for communicating data signals from a first pair of data terminals to a second pair of data terminals of the repeater. In a first channel, an amplifier stage in a receiver amplifies a differential signal received at the first pair of data terminals to generate a differential signal at first and second output nodes of the receiver, and a transmitting circuit transmits a differential signal at the second pair of data terminals responsive to the differential signal at the first and second output nodes of the receiver. The receiver includes a hysteresis stage that receives an offset in opposition to the differential signal at the first and second output nodes of the receiver. End-of-packet (EOP) dribble in USB communications in the HS mode is reduced by the offset at the hysteresis stage.

公开(公告)号：US11309892B2

公开(公告)日：2022-04-19

申请号：US17174119

申请日：2021-02-11

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Win Naing Maung ,  Bharath Kumar Singareddy ,  Soumi Paul ,  Mayank Garg ,  Suzanne Mary Vining

IPC: H04B3/36 ,  G06F13/42 ,  H04L25/02 ,  H03K19/0185 ,  H04L7/00

Abstract: A circuit includes signal conditioner circuitry, level shifter circuitry, and state detector and controller circuitry coupled between the signal conditioner circuitry and the level shifter circuitry. The state detector and controller circuitry includes receiver circuitry and a finite state machine coupled to the receiver circuitry. The finite state machine is configured to detect a first data rate from signals, control operation of the signal conditioner circuitry responsive to detecting the first data rate, and control operation of the level shifter circuitry during a second data rate.

公开(公告)号：US20210294302A1

公开(公告)日：2021-09-23

申请号：US17339213

申请日：2021-06-04

Applicant: Texas Instruments Incorporated

Inventor： Matthew David Romig ,  Mayank Garg

IPC: G05B19/414

Abstract: Methods, systems, and apparatus to facilitate multi-channel isolation is disclosed. An example apparatus includes a multiplexer including a first input terminal, a second input terminal, and an output terminal; a modulator including an input terminal and an output terminal, the input terminal of the modulator coupled to the output terminal of the multiplexer; an isolation capacitor including a first terminal and a second terminal, the first terminal of the isolation capacitor coupled to the output terminal of the modulator; a first receiver die coupled to the second terminal of the isolation capacitor; and a second receiver die coupled to the second terminal of the isolation capacitor.

公开(公告)号：US20210157299A1

公开(公告)日：2021-05-27

申请号：US16692674

申请日：2019-11-22

Applicant: Texas Instruments Incorporated

Inventor： Matthew David Romig ,  Mayank Garg

IPC: G05B19/414

Abstract: Methods, systems, and apparatus to facilitate multi-channel isolation is disclosed. An example apparatus includes a multiplexer including a first input terminal, a second input terminal, and an output terminal; a modulator including an input terminal and an output terminal, the input terminal of the modulator coupled to the output terminal of the multiplexer; an isolation capacitor including a first terminal and a second terminal, the first terminal of the isolation capacitor coupled to the output terminal of the modulator; a first receiver die coupled to the second terminal of the isolation capacitor; and a second receiver die coupled to the second terminal of the isolation capacitor.

公开(公告)号：US20210044294A1

公开(公告)日：2021-02-11

申请号：US17082937

申请日：2020-10-28

Applicant: Texas Instruments Incorporated

Inventor： Mayank Garg ,  Shu-Ing Ju ,  Arun Rao ,  Wei Zhang

IPC: H03K17/687 ,  H03K17/693

Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed for a multi-level turn-off circuit. An example power delivery circuit includes a two-level turn-off circuit to be coupled to a first switch to reduce a first gate voltage of the first switch from a first voltage to a second voltage when a current flowing through the first switch is greater than an over-current threshold, the two-level turn-off circuit including a second switch, a voltage-current-voltage buffer to reduce a second gate voltage of the second switch from a third voltage to a fourth voltage, and a comparator circuit to turn off the second switch when the second gate voltage is the fourth voltage, and a driver to be coupled to the first switch to turn off the first switch when the second gate voltage is the fourth voltage.

公开(公告)号：US20240250715A1

公开(公告)日：2024-07-25

申请号：US18625353

申请日：2024-04-03

Applicant: Texas Instruments Incorporated

Inventor： Srijan Rastogi ,  Mayank Garg ,  Anant Shankar Kamath

IPC: H04B3/36 ,  H03F3/45

CPC classification number: H04B3/36 ,  H03F3/45179

Abstract: Universal Serial Bus (USB) repeater circuits and methods of operating the same for communicating data signals from a first pair of data terminals to a second pair of data terminals of the repeater. In a first channel, an amplifier stage in a receiver amplifies a differential signal received at the first pair of data terminals to generate a differential signal at first and second output nodes of the receiver, and a transmitting circuit transmits a differential signal at the second pair of data terminals responsive to the differential signal at the first and second output nodes of the receiver. The receiver includes a hysteresis stage that receives an offset in opposition to the differential signal at the first and second output nodes of the receiver. End-of-packet (EOP) dribble in USB communications in the HS mode is reduced by the offset at the hysteresis stage.

公开(公告)号：US11669069B2

公开(公告)日：2023-06-06

申请号：US17339213

申请日：2021-06-04

Applicant: Texas Instruments Incorporated

Inventor： Matthew David Romig ,  Mayank Garg

IPC: G05B19/414

CPC classification number: G05B19/4144 ,  G05B2219/34236

Abstract: Methods, systems, and apparatus to facilitate multi-channel isolation is disclosed. An example apparatus includes a multiplexer including a first input terminal, a second input terminal, and an output terminal; a modulator including an input terminal and an output terminal, the input terminal of the modulator coupled to the output terminal of the multiplexer; an isolation capacitor including a first terminal and a second terminal, the first terminal of the isolation capacitor coupled to the output terminal of the modulator; a first receiver die coupled to the second terminal of the isolation capacitor; and a second receiver die coupled to the second terminal of the isolation capacitor.