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    ADJUSTABLE EMBEDDED UNIVERSAL SERIAL BUS 2 LOW-IMPEDANCE DRIVING DURATION
    11.
    发明申请
    ADJUSTABLE EMBEDDED UNIVERSAL SERIAL BUS 2 LOW-IMPEDANCE DRIVING DURATION 审中-公开

    公开(公告)号：US20200057742A1

    公开(公告)日：2020-02-20

    申请号：US16414496

    申请日：2019-05-16

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Win Naing MAUNG ,  Yonghui TANG ,  Huanzhang HUANG ,  Douglas Edward WENTE

    IPC: G06F13/40 ,  G06F13/42

    Abstract: Aspects of the present disclosure provide for a system. In at least some examples, the system includes an embedded Universal Serial Bus 2 (eUSB2) device having a first receiver and a first transmitter, a processor, a second transmitter coupled to the processor, a second receiver coupled to the processor, a drive low circuit coupled to the processor second transmitter, and differential signal lines having a length greater than ten inches. The differential signal lines are coupled at a first end to the first receiver and the first transmitter and at a second end to the second transmitter and the second receiver. The processor is configured to control the drive low circuit to drive the differential signal lines low with a logic ‘0’ to cause the first receiver to receive the logic ‘0’ and a value of a signal present on the differential signal lines to reach about 0 volts.

    LOSS OF SIGNAL DETECTION CIRCUIT
    12.
    发明申请
    LOSS OF SIGNAL DETECTION CIRCUIT 有权

    公开(公告)号：US20210159896A1

    公开(公告)日：2021-05-27

    申请号：US17163894

    申请日：2021-02-01

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Huanzhang HUANG ,  Amit RANE

    IPC: H03K17/00 ,  G06F13/38 ,  H03K19/003 ,  H03K17/56

    Abstract: Aspects of the disclosure provide for a circuit. In some examples, the circuit includes a first inverter coupled between first and second nodes, a second inverter coupled between third and fourth nodes, and a first logic circuit having a first input coupled to the second node, a second input coupled to the fourth node, and an output, a first positive feedback circuit coupled between the first and third nodes and having a control input. The first positive feedback circuit comprises a first switch coupled between the first and fifth nodes and having a control input, a second switch coupled between the third and sixth nodes and having a control input, a third inverter having an input coupled to the sixth node and an output coupled to the fifth node, and a fourth inverter having an input coupled to the fifth node and an output coupled to the sixth node.

    EMBEDDED UNIVERSAL SERIAL BUS 2 REPEATER
    13.
    发明申请
    EMBEDDED UNIVERSAL SERIAL BUS 2 REPEATER 审中-公开

    公开(公告)号：US20200073839A1

    公开(公告)日：2020-03-05

    申请号：US16404494

    申请日：2019-05-06

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Win Naing MAUNG ,  Douglas Edward WENTE ,  Mustafa Ulvi ERDOGAN ,  Huanzhang HUANG ,  Saurabh GOYAL ,  Bhupendra SHARMA

    IPC: G06F13/38 ,  G06F13/42 ,  H04B3/36

    Abstract: Aspects of the disclosure provide for a circuit including a squelch detector having a first input coupled to a first node and configured to receive a positive component of a differential signal with a floating center tap, a second input coupled to a second node and configured to receive a negative component of the differential signal, and an output coupled to a logic circuit, a first resistor coupled between the first node and a third node, a second resistor coupled between the third node and the second node, a third resistor coupled between the first node and a fourth node, a fourth resistor coupled between the fourth node and the second node, a capacitor coupled between the fourth node and a ground terminal, a comparator having a first input coupled to the third node, a second input coupled to a fifth node, and an output coupled to the logic circuit.

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