公开(公告)号：US20160259879A1

公开(公告)日：2016-09-08

申请号：US14790318

申请日：2015-07-02

Applicant: Synopsys, Inc.

Inventor： Malay Ganai ,  Mohamed Shaker Sarwary ,  Maher Mneimneh ,  Paras Mal Jain ,  Mohammad Homayoun Movahed-Ezazi ,  Pronay Kumar Biswas ,  Nishant Gupta

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F2217/62

Abstract: A system and method for netlist clock domain crossing verification leverages RTL clock domain crossing (CDC) verification data and results. The netlist clock domain crossing verification system (NCDC) migrates RTL-level constraints and waivers to the netlist design so that the user does not have to re-enter them. The NCDC checks the netlist and generates a report that compares RTL-level CDC checking results to the netlist-level CDC checking results to make it easy to see new issues. The NCDC receives and stores netlist corrections from user input or automatically corrects certain CDC violations, in the netlist.

Abstract translation: 网表时域交叉验证的系统和方法利用RTL时钟域交叉（CDC）验证数据和结果。 网表时域交叉验证系统（NCDC）将RTL级别约束和放弃迁移到网表设计，以便用户不必重新输入。 NCDC检查网表，并生成一个报告，将RTL级CDC检查结果与网表级CDC检查结果进行比较，以便轻松查看新问题。 NCDC从网络列表中接收并存储用户输入的网表更正或自动更正某些CDC违规行为。

公开(公告)号：US09208272B2

公开(公告)日：2015-12-08

申请号：US14047396

申请日：2013-10-07

Applicant: Synopsys, Inc.

Inventor： Mohamed Shaker Sarwary

IPC: G06F9/455 ,  G06F17/50

CPC classification number: G06F17/5045 ,  G06F17/5031 ,  G06F17/504

Abstract: Timing Constraints are crucial to meet timing requirements of an Integrated Circuit (IC). Timing exceptions are specified so that certain paths of the design of the IC are not timed as they are not relevant for the speed of the IC. If a path is specified as an exception but it is indeed a timing-relevant path then the design may functionally fail due to timing violations ignored by the timing analysis tools. It is therefore extremely important to ensure that all timing exceptions are correctly specified. The Hybrid Timing Exceptions Verification uses static verification as well as dynamic verification to effectively verify correctness of such timing exceptions. The solution pin-points the errors in the exceptions specification with very low number of false errors that would require significant designer inputs and time to manually waive them.

Abstract translation: 时序约束对于满足集成电路（IC）的时序要求至关重要。 规定了定时异常，使IC的设计的某些路径没有计时，因为它们与IC的速度无关。 如果路径被指定为异常，但它确实是一个与时间相关的路径，则设计可能由于时序分析工具忽略的定时违规而在功能上失败。 因此，确保正确指定所有时序异常是非常重要的。 混合定时异常验证使用静态验证以及动态验证来有效地验证这种定时异常的正确性。 解决方案将异常规范中的错误指向非常少的错误错误，这将需要大量的设计人员输入和时间来手动放弃它们。