公开(公告)号：US11861227B2

公开(公告)日：2024-01-02

申请号：US17477865

申请日：2021-09-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Wan-Soo Choi ,  Young Wook Kim ,  Do Hyeon Park

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0679

Abstract: A method of operating a storage device including a non-volatile memory and a multi-core processor with at least two cores includes the following steps: receiving, by a host interface of the storage device, a first command from a host for requesting the non-volatile memory to perform a predetermined memory operation; generating, by a task scheduler of the storage device, first and second tasks from the first memory command; selecting, by the task scheduler, a first core from among the at least two cores based on execution times of the at least two cores; assigning, by the task scheduler, the first and second tasks to the first core; and requesting, by the first core, a subsequent task from the scheduler while the first core processes the first assigned task and loads code for processing the second task.

公开(公告)号：US11435947B2

公开(公告)日：2022-09-06

申请号：US16745451

申请日：2020-01-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wan-Soo Choi ,  Young Wook Kim ,  Dong Eun Shin ,  Yong Chan Jo

IPC: G06F3/06 ,  G06F9/48 ,  G06F9/54

Abstract: A storage device includes an input stage receiving a first command, a queue manager allocating a first queue entry for the first command, a pre-processor storing the first command in the first queue entry and updating a task list with the first command and a core executing the first command in accordance with an order specified in the updated task list. At least one of the queue manager and the pre-processor is implemented in a customized logic circuit.