公开(公告)号：US12040008B2

公开(公告)日：2024-07-16

申请号：US17953068

申请日：2022-09-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seong-Jin Cho

IPC: G11C11/408 ,  G06F12/06 ,  G11C11/406 ,  G11C11/4091 ,  H01L25/18

CPC classification number: G11C11/4085 ,  G06F12/06 ,  G11C11/406 ,  G11C11/4091 ,  H01L25/18

Abstract: A memory device including a memory bank array which includes a first edge memory block, a second edge memory block, and a plurality of memory blocks placed between the first edge memory block and the second edge memory block; a plurality of sense amplifiers between the plurality of memory blocks, and that connect a first bit line of a memory block on one side of each of the plurality of sense amplifiers and a first complementary bit line of a memory block on an other side of each of the plurality of sense amplifiers; a first edge sense amplifier connected to a second bit line and a second complementary bit line of the first edge memory block; and a second edge sense amplifier connected to a third bit line and a third complementary bit line of the second edge memory block.

公开(公告)号：US12020742B2

公开(公告)日：2024-06-25

申请号：US17734508

申请日：2022-05-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Won-Hyung Song ,  Jung Min You ,  Seong-Jin Cho

IPC: G11C11/401 ,  G11C11/4072 ,  G11C11/408 ,  G11C11/4091 ,  G11C11/4093 ,  G11C11/4096

CPC classification number: G11C11/4072 ,  G11C11/4085 ,  G11C11/4087 ,  G11C11/4091 ,  G11C11/4093 ,  G11C11/4096

Abstract: Disclosed is a method for accessing memory cells arranged in rows and columns. The method includes activating a specific row of the rows of the memory cells, and flipping data bits stored in memory cells of the specific row in response to determining that concentrated activation occurs at the specific row.

公开(公告)号：US10404286B2

公开(公告)日：2019-09-03

申请号：US15664295

申请日：2017-07-31

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hoon Sin ,  Sang-Uhn Cha ,  Ye-Sin Ryu ,  Seong-Jin Cho

IPC: G06F11/10 ,  H03M13/29 ,  H03M13/09 ,  H03M13/13

Abstract: A memory module includes data memories and at least one parity memory. Each of the data memories includes a first memory cell array with a first memory region to store data set corresponding to a plurality of burst lengths and a second memory region to store first parity bits to perform error detection/correction associated with the data set. The at least one parity memory includes a second memory cell array with a first parity region to store parity bits associated with user data set corresponding to all of the data set stored in each of the data memories and a second parity region to store second parity bits for error detection/correction associated with the parity bits.