公开(公告)号：US20230276614A1

公开(公告)日：2023-08-31

申请号：US18144958

申请日：2023-05-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seokho SHIN ,  Taegyu KANG ,  Byeungmoo KANG ,  Joongchan SHIN

IPC: H10B12/00

CPC classification number: H10B12/30 ,  H10B12/03 ,  H10B12/05

Abstract: A semiconductor memory device including a substrate; a semiconductor pattern extending in a first horizontal direction on the substrate; bit lines extending in a second horizontal direction on the substrate perpendicular to the first horizontal direction, the bit lines being at a first end of the semiconductor pattern; word lines extending in a vertical direction on the substrate at a side of the semiconductor pattern; a capacitor structure on a second end of the semiconductor pattern opposite to the first end in the first horizontal direction, the capacitor structure including a lower electrode connected to the semiconductor pattern, an upper electrode spaced apart from the lower electrode, and a capacitor dielectric layer between the lower electrode and the upper electrode; and a capacitor contact layer between the second end of the semiconductor pattern and the lower electrode and including a pair of convex surfaces in contact with the semiconductor pattern.

公开(公告)号：US20210125989A1

公开(公告)日：2021-04-29

申请号：US16986367

申请日：2020-08-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Joongchan SHIN ,  Changkyu KIM ,  Hui-Jung KIM ,  Iljae SHIN ,  Taehyun AN ,  Kiseok LEE ,  Eunju CHO ,  Hyungeun CHOI ,  Sung-Min PARK ,  Ahram LEE ,  Sangyeon HAN ,  Yoosang HWANG

IPC: H01L27/108 ,  H01L23/528

Abstract: A three-dimensional semiconductor memory device includes first semiconductor patterns, which are vertically spaced apart from each other on a substrate, each of which includes first and second end portions spaced apart from each other, and first and second side surfaces spaced apart from each other to connect the first and second end portions, first and second source/drain regions disposed in each of the first semiconductor patterns and adjacent to the first and second end portions, respectively, a channel region in each of the first semiconductor patterns and between the first and second source/drain regions, a first word line adjacent to the first side surfaces and the channel regions and vertically extended, and a gate insulating layer interposed between the first word line and the first side surfaces. The gate insulating layer may be extended to be interposed between the first source/drain regions.