公开(公告)号：US10204920B2

公开(公告)日：2019-02-12

申请号：US15095579

申请日：2016-04-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JinTae Kim ,  Jaewan Choi

IPC: H01L27/118 ,  G06F17/50 ,  H01L27/02

Abstract: A semiconductor device including a standard cell for implementing a logic element includes a first active region and a second active region extending in a second direction on a substrate and spaced apart from each other in a first direction perpendicular to the second direction, gate electrodes intersecting the first active region and the second active region, and source regions and drain regions formed on the first and second active regions at both sides of each of the gate electrodes. A boundary of the standard cell has a polygonal shape, excluding a quadrilateral shape, when viewed in a plan view. As a result, an area of the standard cell may be reduced to reduce a size of the semiconductor device.