公开(公告)号：US20230262962A1

公开(公告)日：2023-08-17

申请号：US18107589

申请日：2023-02-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Miso MYUNG ,  Keunnam KIM ,  Euna KIM ,  Huijung KIM ,  Sangho LEE

IPC: H10B12/00

CPC classification number: H10B12/482 ,  H10B12/315 ,  H10B12/34 ,  H10B12/02

Abstract: An integrated circuit device includes a substrate having an active area, bit line structures on the substrate, the bit line structures including an insulating spacer on each sidewall thereof, a buried contact between the bit line structures, the buried contact being connected to the active area, an insulation capping pattern on each of the bit line structures, a barrier conductive layer covering side surfaces of the insulation capping pattern, and an upper surface and side surfaces of the insulating spacer, and a landing pad electrically connected to the buried contact, the landing pad vertically overlapping one of the bit line structures on the insulation capping pattern and the barrier conductive layer.

公开(公告)号：US20220336464A1

公开(公告)日：2022-10-20

申请号：US17530818

申请日：2021-11-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Junhyeok AHN ,  Kiseok LEE ,  Huijung KIM

IPC: H01L27/108

Abstract: A semiconductor device includes: a substrate including a cell area and an interface area; a gate electrode disposed in the substrate within the cell area and extending in a first direction; a plurality of bit lines intersecting the gate electrode and extending in a second direction intersecting the first direction, wherein the plurality of bit lines includes a plurality of first bit lines and a plurality of second bit lines alternately disposed in the first direction; edge spacers disposed within the interface area and contacting the plurality of second bit lines; and edge insulating layers disposed between the edge spacers and contacting the plurality of first bit lines, wherein at least a portion of each of the edge insulating layers is disposed within the interface area.