SYSTEM AND METHOD FOR PROVIDING IN-STORAGE ACCELERATION (ISA) IN DATA STORAGE DEVICES

    公开(公告)号:US20200341933A1

    公开(公告)日:2020-10-29

    申请号:US16928711

    申请日:2020-07-14

    Abstract: A data storage device includes: a data storage medium; a processor comprising a plurality of processor cores; a plurality of application acceleration black-box (AABB) slots including reconfigurable logic blocks, interconnects, and memories; a host interface that receives a host command from a remote application running on a remote host computer, wherein the host command includes an image file including a register-transfer level (RTL) bitstream and a firmware driver; and a configuration controller that downloads the RTL bitstream to an AABB slot of the plurality of AABB slots and reconfigure the AABB slot, and load the firmware driver to a processor core of the processor. The processor core loaded with the firmware driver runs a data acceleration process of the remote application to access and process data stored in the data storage medium using the RTL bitstream downloaded in the AABB slot.

    SYSTEM AND METHOD FOR PROVIDING IN-STORAGE ACCELERATION (ISA) IN DATA STORAGE DEVICES

    公开(公告)号:US20190107956A1

    公开(公告)日:2019-04-11

    申请号:US15921400

    申请日:2018-03-14

    Abstract: A data storage device includes: a data storage medium; a processor comprising a plurality of processor cores; a plurality of application acceleration black-box (AABB) slots including reconfigurable logic blocks, interconnects, and memories; a host interface that receives a host command from a remote application running on a remote host computer, wherein the host command includes an image file including a register-transfer level (RTL) bitstream and a firmware driver; and a configuration controller that downloads the RTL bitstream to an AABB slot of the plurality of AABB slots and reconfigure the AABB slot, and load the firmware driver to a processor core of the processor. The processor core loaded with the firmware driver runs a data acceleration process of the remote application to access and process data stored in the data storage medium using the RTL bitstream downloaded in the AABB slot.

    SYSTEM AND METHOD FOR DISTRIBUTED ERASURE CODING

    公开(公告)号:US20190050289A1

    公开(公告)日:2019-02-14

    申请号:US15789884

    申请日:2017-10-20

    Abstract: A system and method for distributed erasure coding. A plurality of storage devices is directly connected to one or more host computers, without an intervening central controller distributing data to the storage devices and providing data protection. Parity codes are stored in one or more dedicated storage devices or distributed over a plurality of the storage devices. When a storage device receives a write command, it calculates a partial parity code, and, if the parity code for the data being written is on another storage device, sends the partial parity code to the other storage device, which updates the parity code using the partial parity code.

    METHOD AND APPARATUS FOR REDUCING IP ADDRESSES USAGE OF NVME OVER FABRICS DEVICES

    公开(公告)号:US20180167352A1

    公开(公告)日:2018-06-14

    申请号:US15408168

    申请日:2017-01-17

    CPC classification number: H04L61/2521 H04L61/2514 H04L61/2517 H04L69/22

    Abstract: A method includes: receiving a Transmission Control Protocol (TCP)/Internet Protocol (IP) packet from an initiator, wherein the TCP/IP packet includes an IP address of a switch and a port number; looking up an address translation table based on the IP address of the switch and the port number; translating the IP address of the switch to a private IP address based on the port number according to address mapping information stored in the address translation table; and routing the TCP/IP packet to a non-volatile memory express over fabrics (NVMeoF) device having the private IP address. A network address translation (NAT) router implemented in the switch is configured to perform the address translation from the IP address of the switch to the private IP address of the NVMeoF device.

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