公开(公告)号：US20190325939A1

公开(公告)日：2019-10-24

申请号：US16502943

申请日：2019-07-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JoongShik SHIN ,  Byoungil LEE ,  Hyunmog PARK ,  Euntaek JUNG

IPC: G11C11/408 ,  G11C11/06 ,  G11C8/12 ,  G11C8/08 ,  H01L27/11582 ,  H01L21/8239 ,  H01L27/11573 ,  H01L27/11565 ,  G11C8/14 ,  H01L23/528 ,  H01L27/11575

Abstract: A semiconductor memory device includes a substrate, a ground selection line, a word line, an insulating layer, a vertical channel portion, and a first peripheral circuit gate pattern. The substrate includes a cell array region and a peripheral circuit region. The ground selection line is on the cell array region. The word line is on the ground selection line. The insulating layer is between the ground selection line and the word line. The vertical channel portion penetrates the ground selection line, word line, and insulating layer in a direction vertical to a top surface of the substrate. The first peripheral circuit gate pattern is on the peripheral circuit region of the substrate. The insulating layer extends from the cell array region onto the peripheral circuit region to cover a top surface of the first peripheral circuit gate pattern.