公开(公告)号：US20190089338A1

公开(公告)日：2019-03-21

申请号：US15969437

申请日：2018-05-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Min Su Kim ,  Dae Seong Lee

IPC: H03K3/3562

Abstract: A master-slave flip flop includes a master latch and a slave latch which are sequentially disposed on a substrate in a first direction. The master latch includes a first NMOS transistor and a first PMOS transistor each gated by a first clock signal. The first NMOS transistor and the first PMOS transistor share a first gate line extending in a second direction intersecting with the first direction. The slave latch includes a second NMOS transistor and a second PMOS transistor each gated by the first clock signal. The second NMOS transistor and the second NMOS transistor share a second gate line extending in the second direction. The first gate line and the second gate line are electrically connected to each other.