公开(公告)号：US09251904B2

公开(公告)日：2016-02-02

申请号：US14458567

申请日：2014-08-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Doohyun Kim ,  Hyun Jun Yoon ,  Donghun Kwak ,  Kitae Park ,  Changyeon Yu

IPC: G11C29/56 ,  G11C16/26

CPC classification number: G11C16/26 ,  G11C11/5642 ,  G11C16/3418 ,  G11C16/3495 ,  G11C29/52 ,  G11C29/56

Abstract: A nonvolatile memory device may include a memory cell array which is arranged in rows and columns and has multi-level memory cells; a voltage generator providing a plurality of read voltages to a selected row of the memory cell array; and control logic performing a plurality of page read operations using the read voltages. A first read voltage and a second read voltage among the plurality of read voltages are each associated with a higher probability of occurrence of a bit read error than at least one other read voltage among the plurality of read voltages. The control logic uses the first read voltage and the second read voltage in different page read operations than each other.

Abstract translation: 非易失性存储器件可以包括以行和列布置并具有多级存储单元的存储单元阵列; 电压发生器，向存储单元阵列的选定行提供多个读取电压; 以及控制逻辑，使用读取的电压执行多个页面读取操作。 多个读取电压之间的第一读取电压和第二读取电压各自与多个读取电压中的至少一个其他读取电压的比特读取错误的发生概率相关。 控制逻辑在彼此不同的页读操作中使用第一读电压和第二读电压。