公开(公告)号：US20230130702A1

公开(公告)日：2023-04-27

申请号：US17959812

申请日：2022-10-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Keunwook SHIN ,  Sungtae KIM ,  Alum JUNG

IPC: H01L23/532

Abstract: Provided are an interconnect structure and an electronic device including the same. The interconnect structure may include a first dielectric layer including a trench, a conductive wire filling an inside of trench, and a cap layer on a top surface of the conductive wire. The cap layer may include graphene doped with a group V element. A second dielectric layer may be on a top surface of the first cap layer.

公开(公告)号：US20230096121A1

公开(公告)日：2023-03-30

申请号：US17882169

申请日：2022-08-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Alum JUNG ,  Kyung-Eun BYUN ,  Keunwook SHIN

IPC: H01L29/06 ,  H01L21/02

Abstract: A stacked structure may include a first material layer, a two-dimensional material layer on the first material layer, and a second material layer on the two-dimensional material layer. The two-dimensional material layer may include a plurality of holes that each expose a portion of the first material layer. The second material layer may be coupled to the first material layer through the plurality of holes.

公开(公告)号：US20230081646A1

公开(公告)日：2023-03-16

申请号：US17902111

申请日：2022-09-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Changhyun KIM ,  Unki KIM ,  Alum JUNG ,  Kyung-Eun BYUN

IPC: H01L29/08 ,  H01L29/06 ,  H01L29/161 ,  H01L29/423 ,  H01L29/775 ,  H01L21/02 ,  H01L21/306 ,  H01L29/66

Abstract: A multi bridge channel field effect transistor includes a substrate, a first source/drain pattern on the substrate, a second source/drain pattern apart from the first source/drain pattern in a first direction on the substrate, a first channel layer and a second channel layer between the first source/drain pattern and the second source/drain pattern, a first graphene barrier between the first channel layer and the first source/drain pattern, a gate insulating layer surrounding the first channel layer, and a gate electrode surrounding the first channel layer with the gate insulating layer therebetween.

公开(公告)号：US20190016906A1

公开(公告)日：2019-01-17

申请号：US15944920

申请日：2018-04-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minsu SEOL ,  Sangwon KIM ,  Hyeonjin SHIN ,  Dongwook LEE ,  Seongjun PARK ,  Yunseong LEE ,  Seongjun JEONG ,  Alum JUNG

IPC: C09D7/63 ,  C07F3/02 ,  G03F7/16 ,  G03F7/20 ,  G03F7/38 ,  G03F7/32 ,  H01L21/311 ,  H01L21/3213

Abstract: Provided are a hardmask composition including a structure represented by Formula 1 and a solvent, a method of forming a pattern using the hardmask composition, and a hardmask formed from the hardmask composition. wherein in Formula 1, R1 to R8, X, and M are described in detail in the detailed description.