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11.发明公开公开(公告)号：US20240298377A1
公开(公告)日：2024-09-05
申请号：US18647556
申请日：2024-04-26
Applicant: Samsung Electronics Co., Ltd.
Inventor： Kyunghoon LEE , Hyejeong KIM , Moongyo BAE , Soomin LEE
Abstract: An electronic device is provided. The electronic device includes memory storing one or more computer programs, and one or more processors communicatively coupled to the memory, wherein the one or more computer programs include computer-executable instructions that, when executed by the one or more processors, cause the electronic device to identify expiration of a first timer having an expiration time shorter than a radio resource control (RRC) inactivity timer set by a network in an RRC_CONNECTED state, identify an accumulated count of expiration of the RRC inactivity timer during a past first period from a time of expiration of the first timer, based on the accumulated count of expiration of the RRC inactivity timer expiration of the first timer, identify whether a UEAssistanceInformation message including a preferredRRC-State information element is transmittable, when the UEAssistanceInformation message including the preferredRRC-State information element is not transmittable, identify whether the RRC inactivity timer starting simultaneously with the first timer expires, based on expiration of the RRC inactivity timer, change an RRC state from the RRC_CONNECTED state to an RRC_INACTIVE state or an RRC_IDLE state, and when the UEAssistanceInformation message including the preferredRRC-State information element is transmittable, transmit, to the network, the UEAssistanceInformation message including the preferredRRC-State information element for causing the change of the RRC state from the RRC_CONNECTED state to the RRC_INACTIVE state or the RRC_IDLE state.
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公开(公告)号：US20230171134A1
公开(公告)日：2023-06-01
申请号：US17951482
申请日：2022-09-23
Applicant: Samsung Electronics Co., Ltd.
Inventor： Jahoon JIN , Kyunghwan MIN , Soomin LEE , Sang-Ho KIM , Jihoon LIM , Sodam JU , Hyun Su CHEA
CPC classification number: H04L25/03878 , H04L7/0079 , H04L1/205 , H04B1/16
Abstract: A semiconductor device including a comparison circuit configured to receive an input signal having n signal levels, where n is a natural number equal to or greater than three, and output n-1 first signals having two signal levels. The device includes a jitter compensation circuit configured to receive the n-1 first signals and compensate for at least one of a length of a period in which a signal level of at least one of the n-1 first signals transitions from a first signal level to a second signal level different from the first signal level, and a length of a period in which the signal level of the at least one of the n-1 first signals transitions from the second signal level to the first signal level, to output n-1 second signals.
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13.发明申请公开(公告)号：US20210392649A1
公开(公告)日：2021-12-16
申请号：US17285528
申请日：2019-11-15
Applicant: Samsung Electronics Co., Ltd.
Inventor： Junsuk KIM , Sangho LEE , Soomin LEE , Wonsuk CHUNG , Suyoung PARK
Abstract: An electronic device, according to various embodiments of the present invention, may comprise: a first communication circuit configured to provide first wireless communication using a first frequency band; a second communication circuit configured to provide second wireless communication using a second frequency band; a processor operatively connected with the first communication circuit and the second communication circuit; and a memory operatively connected with the processor, and configured to store information about the first frequency band and the second frequency band, wherein the memory can store instructions configured to, when executed, enable the processor to communicate with a first base station using the first communication circuit, to receive a first signal from the first base station, and to receive a second signal from a second base station using the second communication circuit on the basis of information on the frequency band while communicating with the first base station, and to select one of a single uplink operation or a dual uplink operation on the basis of information obtained or measured in response to receiving the first signal or the second signal.
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公开(公告)号：US20210249064A1
公开(公告)日：2021-08-12
申请号：US17245064
申请日：2021-04-30
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Kihwan SEONG , Soomin LEE , Sanghune PARK
IPC: G11C11/4076 , G06F11/10
Abstract: A memory controller includes a clock signal generator generating a clock signal; a first data receiving circuit receiving a serial signal having a plurality of logic values from a memory, using the serial signal to compensate for a phase error of the clock signal, and generating a phase-compensated clock signal as a first clock signal; and at least one second data receiving circuit receiving data from the memory, receiving the first clock signal from the first data receiving circuit, and using the first clock signal to recover the data.
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15.发明申请公开(公告)号：US20210227623A1
公开(公告)日：2021-07-22
申请号：US17057213
申请日：2019-05-16
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Suyoung PARK , Suha YOON , Euichang JUNG , Hongju PARK , Sunghyuk SHIN , Soomin LEE , Jangbok LEE
Abstract: The present disclosure relates to a 5G or pre-5G communication system for supporting higher data transmission rate beyond a 4G communication systems such as LTE. A method by a terminal in a wireless communication system according to an embodiment of the present invention comprises the steps of: deciding the release of the connection to a secondary node; generating a connection release request message for requesting the connection release; and transmitting the connection release request message.
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Patent Agency Ranking
16.发明申请公开(公告)号：US20200229079A1
公开(公告)日：2020-07-16
申请号：US16742805
申请日：2020-01-14
Applicant: Samsung Electronics Co., Ltd
Inventor： Soomin LEE , Seonmi KIM , Kyunghoon LEE , Hyejeong KIM , Sangho LEE , Sunmin HWANG
Abstract: An electronic device is disclosed. The electronic device includes a wireless communication circuitry, a processor operatively connected with the wireless communication circuitry, and a memory, operatively connected with the processor, storing configured network slice selection assistance information (NSSAI) and an application. The memory stores instructions, when executed, causing the processor to, when the electronic device is booted, identify a single-NSSAI (s-NSSAI) candidate group including at least one s-NSSAI, based on configuration information of the application, determine a specified number of s-NSSAIs among at least one s-NSSAI included in the configured NSSAI as a first requested NSSAI based on the number of s-NSSAIs included in the configured NSSAI and the s-NSSAI candidate group, and transmit a first registration request message including the first requested NSSAI, via the wireless communication circuitry.
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公开(公告)号：US20240303214A1
公开(公告)日：2024-09-12
申请号：US18458332
申请日：2023-08-30
Applicant: Samsung Electronics Co., Ltd.
Inventor： Jahoon JIN , Kyunghwan MIN , Sangho KIM , Hyoungjoong KIM , Soomin LEE , Sodam JU
CPC classification number: G06F13/4282 , H03K5/24 , G06F2213/0002
Abstract: Disclosed is a receiver of a serial interface, comprising, a first multiplexer configured to select one of a data signal and a first reference voltage in response to an enable signal, a second multiplexer configured to select one of the first reference voltage and a second reference voltage in response to the enable signal, a comparator receiving an output of the first multiplexer to a positive input terminal and an output of the second multiplexer to a negative input terminal, and a reference generator configured to generate the second reference voltage and to generate the first reference voltage from the second reference voltage using an unity gain buffer.
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公开(公告)号：US20240267197A1
公开(公告)日：2024-08-08
申请号：US18472796
申请日：2023-09-22
Applicant: Samsung Electronics Co., Ltd.
Inventor： Kyunghwan MIN , Sangho KIM , Soomin LEE , Sodam JU , Jahoon JIN
CPC classification number: H04L7/0337 , H04L7/0091
Abstract: Provided is a method of correcting a clock, the method including receiving a first clock, a second clock, a third clock, and a fourth clock, correcting each of a second rising edge of the second clock, a third rising edge of the third clock, and a fourth rising edge of the fourth clock based on a first rising edge of the first clock, and correcting each of a first falling edge of the first clock, a second falling edge of the second clock, a third falling edge of the third clock, and a fourth falling edge of the fourth clock based on a first rising edge of the first clock.
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公开(公告)号：US20220272652A1
公开(公告)日：2022-08-25
申请号：US17667107
申请日：2022-02-08
Applicant: Samsung Electronics Co., Ltd.
Inventor： Injae SONG , Dongho KIM , Soomin LEE
Abstract: An electronic device is provided. The electronic device includes at least one processor, which may be configured to establish at least one first protocol data unit (PDU) session in a state of being registered in a 5th generation system (5GS), store first information related to the at least one first PDU session, perform a procedure for registering with an evolved packet system (EPS), based on at least one first trigger causing a system fallback from the 5GS to the EPS, perform a procedure for registering with the 5GS, based on at least one second trigger causing a return to the 5GS, compare second information related to a second PDU session, with the first information, perform an operation of establishing, a third PDU session when the third PDU session not comprised in the second PDU session is identified, and perform an operation of modifying, a fourth PDU session.
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公开(公告)号：US20210250161A1
公开(公告)日：2021-08-12
申请号：US17219187
申请日：2021-03-31
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Soomin LEE , Kihwan SEONG
Abstract: A method of calibrating a clock phase and a voltage offset includes receiving an input data signal that is periodically toggled. A clock phase calibration operation is performed based on an up signal and a down signal, such that phases of a plurality of clock signals are adjusted. The up signal and the down signal are generated based on the input data signal, a reference voltage and the plurality of clock signals. A voltage offset calibration operation is performed based on the up signal, the down signal and a first sample data signal, such that a voltage level of the reference voltage is adjusted. The first sample data signal is generated by sampling the input data signal based on one of the plurality of clock signals. The clock phase calibration operation and the voltage offset calibration operation are performed independently of each other and not to overlap with each other.
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