公开(公告)号：US10607530B2

公开(公告)日：2020-03-31

申请号：US15819367

申请日：2017-11-21

Applicant: Samsung Display Co., Ltd.

Inventor： Shimho Yi ,  Sung-In Kang ,  Kyunho Kim ,  Seunghwan Moon

IPC: G09G3/30 ,  G09G3/36 ,  G09G3/20 ,  G05F3/24 ,  G09G3/00

Abstract: A power voltage generating circuit includes an input part, a clock determining part and a plurality of switches. The input part receives a plurality of clock signals and generates a plurality of peak signals corresponding to rising edges of the plurality of clock signals. The clock determining part determines a normal mode and an abnormal mode based on a number of the plurality of peak signals. The switches blocks outputs of the plurality of clock signals in the abnormal mode.

公开(公告)号：US10217431B2

公开(公告)日：2019-02-26

申请号：US15380804

申请日：2016-12-15

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Kyunho Kim ,  Sung-In Kang ,  Seunghwan Moon

IPC: G09G3/36

Abstract: A display apparatus includes a display panel having fan-out lines, data lines, a first dummy line, and a second dummy line. The fan-out lines are sequentially disposed along a first direction. The data lines are connected to the fan-out lines at first through nodes. The first dummy line is connected to one of the nodes. The second dummy line is connected to another of the nodes. A first data driver is configured to output data voltages to some of the fan-out lines based on a data signal. A second data driver is configured to output voltages to other fan-out lines based on the data signal. A timing controller is configured to compensate the data signal based on a voltage of nodes that the dummy lines are connected to.