公开(公告)号：US11251258B2

公开(公告)日：2022-02-15

申请号：US16118776

申请日：2018-08-31

Applicant: Samsung Display Co., Ltd.

Inventor： Seunghwan Cho ,  Jonghyun Choi ,  Kyunghoon Kim ,  Donghwan Shim ,  Seonyoung Choi

IPC: H01L27/32 ,  H01L51/52 ,  G09G3/3225 ,  H01L51/50 ,  H01L51/00

Abstract: A display apparatus includes a substrate including a display area including a main display area and an edge display area extended directly from a side of the main display area, and a peripheral area outside the display area and including a pad area through which electrical signals are applied to the display area; and in the peripheral area, a plurality of wirings between the display area and the pad area and through which the electrical signals are transmitted from the pad area to the display area, the plurality of wirings including: a first wiring through which an electrical signal is transmitted from the pad area to the main display area, and a second wiring through which an electrical signal is transmitted from the pad area to the edge display area, where an electrical resistance per unit length of the first wiring is greater than that of the second wiring.

公开(公告)号：US11211446B2

公开(公告)日：2021-12-28

申请号：US16118776

申请日：2018-08-31

Applicant: Samsung Display Co., Ltd.

Inventor： Seunghwan Cho ,  Jonghyun Choi ,  Kyunghoon Kim ,  Donghwan Shim ,  Seonyoung Choi

IPC: H01L27/32 ,  H01L51/52 ,  G09G3/3225 ,  H01L51/50 ,  H01L51/00

Abstract: A display apparatus includes a substrate including a display area including a main display area and an edge display area extended directly from a side of the main display area, and a peripheral area outside the display area and including a pad area through which electrical signals are applied to the display area; and in the peripheral area, a plurality of wirings between the display area and the pad area and through which the electrical signals are transmitted from the pad area to the display area, the plurality of wirings including: a first wiring through which an electrical signal is transmitted from the pad area to the main display area, and a second wiring through which an electrical signal is transmitted from the pad area to the edge display area, where an electrical resistance per unit length of the first wiring is greater than that of the second wiring.

公开(公告)号：US20210091160A1

公开(公告)日：2021-03-25

申请号：US16821424

申请日：2020-03-17

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： MINKU LEE ,  Kyunghoon Kim ,  Mihae Kim ,  Changwon Jeong ,  Wonmi Hwang

IPC: H01L27/32 ,  H01L51/00 ,  H01L51/52

Abstract: A display panel includes: a substrate including an opening area, a non-display area at least partially surrounding the opening area, and a display area; a plurality of first lines, each of which includes a first bypass portion along the opening area; a plurality of second lines, each of which includes a second bypass portion along the opening area; and a shield layer overlapping at least one first bypass portion. Each of the first lines includes a first or second conductive line in the non-display area. Each of the first and second conductive lines includes the first bypass portion. The first and second conductive lines are alternately arranged and are disposed on different layers. Each of the second lines includes a third conductive line in the non-display area. Each of the third conductive lines includes the second bypass portion, and at least partially overlaps the first or second conductive line.

公开(公告)号：US09978328B2

公开(公告)日：2018-05-22

申请号：US15019741

申请日：2016-02-09

Applicant: Samsung Display Co., Ltd.

Inventor： Sehyoung Cho ,  Kyunghoon Kim ,  Dongwoo Kim ,  Ilgon Kim ,  Kangmoon Jo ,  Hyunjoon Kim

IPC: G09G3/36

CPC classification number: G09G3/3677 ,  G09G2310/0286

Abstract: There is provided a scan driver. The scan driver includes stages. An ith (i is a natural number) stage circuit includes an output unit, a controller configured to control the voltage of the second node in response to a kth (k is a natural number) clock signal supplied to a second input terminal, and an input unit configured to control the voltages of the first node and the second node in response to a carry signal of a previous stage that is supplied to a third input terminal and a carry signal of at least one next stage. The kth clock signal maintains a gate on voltage at a point of time at which a voltage of the jth clock signal is changed to a gate on voltage.