公开(公告)号：US11961849B2

公开(公告)日：2024-04-16

申请号：US17342088

申请日：2021-06-08

Applicant: Samsung Display Co., LTD.

Inventor： Keum Hee Lee ,  Dong Hoon Shin ,  June Whan Choi ,  Seung Sok Son ,  Woo Geun Lee

IPC: H01L27/12

CPC classification number: H01L27/1248 ,  H01L27/124

Abstract: A display device includes a base layer; a first pattern disposed on the base layer; an insulating layer disposed on the first pattern and including layers; and a second pattern disposed on the insulating layer. At least two of the layers of the insulating layer include a same material.

公开(公告)号：US11948510B2

公开(公告)日：2024-04-02

申请号：US18064813

申请日：2022-12-12

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Soojung Chae ,  Seokhwan Bang ,  Seokje Seong ,  Jinseok Oh ,  Woobin Lee ,  June Whan Choi

IPC: G09G3/32 ,  G09G3/3233

CPC classification number: G09G3/3233 ,  G09G2300/0426 ,  G09G2300/0809

Abstract: A pixel circuit includes a first driving transistor including a gate electrode connected to a first node, a first electrode to receive a first power voltage, and a second electrode connected to a second node, a second driving transistor including a gate electrode and a second electrode connected to the second node, a first electrode to receive the first power voltage, and a back gate electrode connected to the first node, a write transistor including a first electrode to receive a data voltage and a second electrode connected to the first node, an initialization transistor including a gate electrode to receive an initialization gate signal, a first electrode to receive an initialization voltage, and a second electrode connected to the second node, a storage capacitor connected to the first and second nodes, and a light emitting element connected to the second node and configured to receive a second power voltage.

公开(公告)号：US10032803B2

公开(公告)日：2018-07-24

申请号：US15343780

申请日：2016-11-04

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Zhu Xun ,  Jae Woo Park ,  Jae Won Song ,  Keum Hee Lee ,  June Whan Choi

IPC: H01L21/00 ,  H01L31/00 ,  H01L27/12 ,  H01L29/417 ,  H01L21/443 ,  H01L29/45 ,  H01L29/66 ,  H01L29/786 ,  H01L21/768 ,  H01L23/532 ,  G02F1/1335 ,  G02F1/1368

Abstract: A thin film transistor array panel is provided as follows. A gate electrode is disposed on a substrate. A semiconductor layer is disposed on the gate electrode. A gate insulating layer is disposed between the gate electrode and the semiconductor layer. A source electrode is disposed on a first side of the semiconductor layer, having a first lateral surface. A drain electrode is disposed on a second side of the semiconductor layer, having a second lateral surface. The first and second lateral surfaces define a spacing which overlaps the gate electrode. A metal suicide layer is disposed on the first and second lateral surfaces. A passivation layer is disposed on the metal silicide layer, the source electrode and the drain electrode. The passivation layer is not in contact with the first and second lateral surfaces.

公开(公告)号：US09136342B2

公开(公告)日：2015-09-15

申请号：US14495835

申请日：2014-09-24

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Yeon Taek Jeong ,  Bo Sung Kim ,  Doo-Hyoung Lee ,  June Whan Choi ,  Tae-Young Choi ,  Kano Masataka

IPC: H01L29/76 ,  H01L29/423 ,  H01L29/51 ,  H01L29/49 ,  H01L29/786

CPC classification number: H01L29/42384 ,  H01L29/4908 ,  H01L29/51 ,  H01L29/512 ,  H01L29/786 ,  H01L2029/42388

Abstract: A thin film transistor is provided. A thin film transistor according to an exemplary embodiment of the present invention includes: a substrate; a gate line disposed on the substrate and including a gate electrode; a semiconductor layer disposed on the substrate and including at least a portion overlapping the gate electrode; a gate insulating layer disposed between the gate line and the semiconductor layer; and a source electrode and a drain electrode disposed on the substrate and facing each other over a channel region of the semiconductor layer. The gate insulating layer includes a first region and a second region, the first region corresponds to the channel region of the semiconductor layer, the first region is made of a first material, the second region is made of a second material, and the first material and the second material have different atomic number ratios of carbon and silicon.

Abstract translation: 提供薄膜晶体管。 根据本发明的示例性实施例的薄膜晶体管包括：基板; 栅极线，设置在所述基板上并且包括栅电极; 半导体层，设置在所述基板上，并且至少包括与所述栅电极重叠的部分; 设置在所述栅极线和所述半导体层之间的栅极绝缘层; 以及设置在所述基板上并且在所述半导体层的沟道区域上彼此面对的源电极和漏电极。 栅极绝缘层包括第一区域和第二区域，第一区域对应于半导体层的沟道区域，第一区域由第一材料制成，第二区域由第二材料制成，第一材料 并且第二材料具有不同的碳和硅原子数比。