公开(公告)号：US12101104B2

公开(公告)日：2024-09-24

申请号：US17721110

申请日：2022-04-14

Applicant: STMICROELECTRONICS S.r.l.

Inventor： Roberto Modaffari ,  Paolo Pesenti

IPC: H03M3/00

CPC classification number: H03M3/384 ,  H03M3/422 ,  H03M3/436 ,  H03M3/464 ,  H03M3/496

Abstract: A delta-sigma modulator includes a quantizer, a signal propagation path including a plurality of cascaded integrators coupled between the input node and the quantizer, and a feedback network including a plurality of digital-to-analog converters. In a calibration mode of operation, a first digital-to-analog converter of the plurality of digital-to-analog converters of the feedback network receives a signal including a periodic alternated digital sequence, the first digital-to-analog converter being coupled to a first integrator of the plurality of cascaded integrators, integrators of the plurality of cascaded integrators other than the first integrator operate in a gain mode of operation, the delta-sigma modulator generates a digital test signal at an output of the quantizer based on the signal including the periodic alternated digital sequence, and calibration circuitry generates a calibration signal based on the digital test signal and a reference digital word.

公开(公告)号：US11290124B2

公开(公告)日：2022-03-29

申请号：US17163230

申请日：2021-01-29

Applicant: STMICROELECTRONICS S.r.l.

Inventor： Roberto Modaffari ,  Paolo Pesenti ,  Germano Nicollini

IPC: H03M3/00

Abstract: A delta-sigma modulation circuit has a sampling period and, in operation, generates a delta-sigma modulated signal based on the analog input signal. The delta-sigma modulation circuit includes: a first integrator; an analog-to-digital converter; a feedback-loop coupled between an input of the first integrator and the output interface; a second integrator coupled between the first integrator and the analog-to-digital converter. The delta-sigma modulation circuit has loop-delay compensation circuitry having a plurality of switches. The loop delay compensation circuitry, in operation, controls the plurality of switches based on a time interval of a duration of half the sampling period and generates a loop-delay compensation signal.

公开(公告)号：US20180274941A1

公开(公告)日：2018-09-27

申请号：US15919882

申请日：2018-03-13

Applicant: STMicroelectronics S.r.l.

Inventor： Matteo Quartiroli ,  Alessandro Mecchia ,  Paolo Pesenti ,  Stefano Facchinetti ,  Andrea Donadel

IPC: G01C25/00 ,  G01C19/5776

CPC classification number: G01C25/005 ,  G01C19/5776

Abstract: A demodulator for demodulating the in-phase component of an input signal which is in-phase and quadrature modulated. The demodulator includes a register storing a phase calibration value and a temperature sensor that performs a plurality of temperature sensings. A compensating stage generates for each temperature sensed a corresponding first sample on the basis of the difference between the sensed temperature and a calibration temperature and a compensation function indicative of a relationship existing between the phase of the input signal and the temperature. A combination stage generates a plurality of second samples, each second sample being a function of the phase calibration value and a corresponding first sample. A generating stage generates a demodulating signal having a phase which depends on the second samples and a demodulating stage demodulates the input signal by means of the demodulating signal.