公开(公告)号：US20190007038A1

公开(公告)日：2019-01-03

申请号：US15946506

申请日：2018-04-05

Applicant: STMicroelectronics (Grenoble 2) SAS ,  STMicroelectronics (Rousset) SAS

Inventor： Vincent Binet ,  David Chesneau

IPC: H03K5/24 ,  H03K19/20 ,  H03F3/19

CPC classification number: H03K5/24 ,  H03F3/19 ,  H03K3/02337 ,  H03K5/1252 ,  H03K19/20 ,  H03K2005/00019

Abstract: A comparison circuit includes an input interface configured to receive input signals and an output interface configured to deliver an output signal. A comparator is coupled between the input interface and the output interface. An amplifier is coupled between the input interface and the comparator. A neutralization circuit is configured to neutralize any change of state of the output signal starting from each moment in time at which the change of state of the output signal occurs and lasting for a second duration of propagation that compensates for a duration of propagation of signals within the amplifier.

公开(公告)号：US12176804B2

公开(公告)日：2024-12-24

申请号：US17647133

申请日：2022-01-05

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Sebastien Ortet ,  Vincent Binet

IPC: H02M1/36 ,  H02M1/00 ,  H02M3/158

Abstract: The present disclosure relates to a voltage converter and method for pulse frequency modulation-type operation during a start-up phase.

公开(公告)号：US11581880B2

公开(公告)日：2023-02-14

申请号：US17524306

申请日：2021-11-11

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Vincent Binet ,  Michel Cuenca ,  Ludovic Girardeau

IPC: H03K4/50 ,  H03K5/24

Abstract: Series of first ramps and second ramps are generated. A circuit delivers a first signal representative of the comparison of each first ramp with a set point and delivers a second signal representative of the comparison of each second ramp with the set point. Based on the first and second signals: a first ramp is stopped and a second ramp is started when the first ramp reaches the set point, and a second ramp is stopped and a first ramp is started when the second ramp reaches the set point. The value of the set point is modulated in response a maximum value of the first/second last ramp compared with the set point.

公开(公告)号：US20200014376A1

公开(公告)日：2020-01-09

申请号：US16449700

申请日：2019-06-24

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Yohan Joly ,  Vincent Binet

IPC: H03K5/24 ,  H03F3/45 ,  H03K3/3565

Abstract: A comparator includes a folded cascode stage having positive and negative outputs. The folded cascode stage includes: a common-mode voltage regulation circuit that includes resistive elements that are respectively situated between each of the outputs and a common-mode node. A compensation circuit is configured to regulate a difference between the voltages on the outputs, and is configured to generate a constant and continuous compensation current in the two resistive elements. A hysteresis circuit is configured to offset voltages on the outputs, and to generate a hysteresis current in the two resistive elements.