公开(公告)号：US11424765B2

公开(公告)日：2022-08-23

申请号：US16883845

申请日：2020-05-26

Applicant: SK hynix Inc.

Inventor： Won Gyu Shin

IPC: H03M13/15

Abstract: An error correction code (ECC) decoder includes a syndrome calculation block and a path controller. The syndrome calculation block is configured to perform a syndrome calculation for generating a syndrome from a codeword. The path controller is configured to output data transmitted through first to third paths. The first path is a path for transmitting the codeword to the path controller when no error is detected. The second path includes a single-error decoding logic circuit, and the single-error decoding logic circuit corrects a single error of the codeword to transmit the corrected codeword to the path controller through the second path. The third path includes a multi-error decoding logic circuit, and the multi-error decoding logic circuit corrects at least two errors of the codeword to transmit the corrected codeword to the path controller.

公开(公告)号：US11048586B2

公开(公告)日：2021-06-29

申请号：US16883783

申请日：2020-05-26

Applicant: SK hynix Inc.

Inventor： Won Gyu Shin ,  Jung Hyun Kwon ,  Jin Woong Suh ,  Do Sun Hong

IPC: G06F11/00 ,  G06F11/10 ,  H03M13/15

Abstract: A memory system includes a memory medium, a loop-buffer configured to store read data outputted from the memory medium in a first operation mode, a fake-command generator configured to generate a fake-command in a second operation mode, and an error correction code (ECC) decoder configured to perform an ECC decoding operation of the read data stored in the loop-buffer in response to the fake-command.

公开(公告)号：US20200210292A1

公开(公告)日：2020-07-02

申请号：US16585564

申请日：2019-09-27

Applicant: SK hynix Inc.

Inventor： Dae Sung Kim ,  Won Gyu Shin

IPC: G06F11/10 ,  H03M13/15

Abstract: An error correction apparatus may include: an input component configured to receive data; an error information generation component having a first error detection ability to detect L errors and a second error detection ability to detect K errors, where L is a positive integer and K is an integer larger than L, and configured to generate error information including the number of errors contained in the received data and the positions of the errors, based on the first error detection ability, and generate the error information based on the second error detection ability, when the error information is not generated on the basis of the first error detection ability; an error correction component configured to correct the errors of the received data based on the generated error information; and an output component configured to output the corrected data.