公开(公告)号：US20210216243A1

公开(公告)日：2021-07-15

申请号：US17014667

申请日：2020-09-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyunsung SHIN ,  Sanghyuk KWON ,  Youngcheon KWON ,  Sukhan LEE ,  Haesuk LEE

IPC: G06F3/06 ,  G06N3/02

Abstract: A memory device includes a memory bank including a plurality of banks, each including a memory cell array; a calculation logic including a plurality of processor-in-memory (PIM) circuits arranged in correspondence to the banks, each of the plurality of PIM circuits performing calculation processing using at least one selected from data provided from a host and information read from a corresponding bank among the banks; and a control logic configured to control a memory operation on the memory bank in response to a command and/or an address, each received from the host, or to control the calculation logic to perform the calculation processing, wherein reading operations are respectively performed in parallel on the banks for the calculation processing, offsets having different values are respectively configured for the banks, and information is read from different positions in respective memory cell arrays of the banks and provided to the PIM circuits.