公开(公告)号：US20180032260A1

公开(公告)日：2018-02-01

申请号：US15282848

申请日：2016-09-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Krishna MALLADI ,  Jongmin GIM ,  Hongzhong ZHENG

IPC: G06F3/06 ,  G06F12/02

CPC classification number: G06F12/08 ,  G06F12/0868 ,  G06F12/10 ,  G06F2212/1016 ,  G06F2212/152 ,  G06F2212/401 ,  G06F2212/403

Abstract: A memory device includes a memory interface to a host computer and a memory overprovisioning logic configured to provide a virtual memory capacity to a host operating system (OS). A kernel driver module of the host OS is configured to manage the virtual memory capacity of the memory device provided by the memory overprovisioning logic of the memory device and provide a fast swap of anonymous pages to a frontswap space and file pages to a cleancache space of the memory device based on the virtual memory capacity of the memory device.

公开(公告)号：US20220035719A1

公开(公告)日：2022-02-03

申请号：US17499852

申请日：2021-10-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dimin NIU ,  Krishna MALLADI ,  Hongzhong ZHENG

IPC: G06F11/20 ,  G06F11/10

Abstract: According to one general aspect, an apparatus may include a plurality of stacked integrated circuit dies that include a memory cell die and a logic die. The memory cell die may be configured to store data at a memory address. The logic die may include an interface to the stacked integrated circuit dies and configured to communicate memory accesses between the memory cell die and at least one external device. The logic die may include a reliability circuit configured to ameliorate data errors within the memory cell die. The reliability circuit may include a spare memory configured to store data, and an address table configured to map a memory address associated with an error to the spare memory. The reliability circuit may be configured to determine if the memory access is associated with an error, and if so completing the memory access with the spare memory.

公开(公告)号：US20200004652A1

公开(公告)日：2020-01-02

申请号：US16150239

申请日：2018-10-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dimin NIU ,  Krishna MALLADI ,  Hongzhong ZHENG

IPC: G06F11/20 ,  G06F3/06

Abstract: According to one general aspect, an apparatus may include a plurality of stacked integrated circuit dies that include a memory cell die and a logic die. The memory cell die may be configured to store data at a memory address. The logic die may include an interface to the stacked integrated circuit dies and configured to communicate memory accesses between the memory cell die and at least one external device. The logic die may include a reliability circuit configured to ameliorate data errors within the memory cell die. The reliability circuit may include a spare memory configured to store data, and an address table configured to map a memory address associated with an error to the spare memory. The reliability circuit may be configured to determine if the memory access is associated with an error, and if so completing the memory access with the spare memory.

公开(公告)号：US20180122456A1

公开(公告)日：2018-05-03

申请号：US15426033

申请日：2017-02-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Shaungchen LI ,  Dimin NIU ,  Krishna MALLADI ,  Hongzhong ZHENG

IPC: G11C11/406

CPC classification number: G11C11/40622 ,  G06F9/38 ,  G06F12/00 ,  G06F15/7821 ,  G06F15/80 ,  G11C7/1006 ,  G11C7/1012 ,  G11C11/405 ,  G11C11/4076 ,  G11C11/4091 ,  G11C11/4096

Abstract: A dynamic random access memory (DRAM) processing unit (DPU) may include at least one computing cell array having a plurality of DRAM-based computing cells arranged in an array having at least one column in which the at least one column may include at least three rows of DRAM-based computing cells configured to provide a logic function that operates on a first and a second row of the at least three rows and configured to store a result of the logic function in a third row of the at least three rows; and a controller that may be coupled to the at least one computing cell array to configure the at least one computing cell array to perform a DPU operation.

公开(公告)号：US20170040050A1

公开(公告)日：2017-02-09

申请号：US15299445

申请日：2016-10-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Mu-Tien CHANG ,  Krishna MALLADI ,  Dimin NIU ,  Hongzhong ZHENG

IPC: G11C11/406 ,  G11C11/4076

CPC classification number: G11C11/40615 ,  G06F13/1636 ,  G11C5/04 ,  G11C11/40618 ,  G11C11/4076

Abstract: A memory (1205) is disclosed. The memory (1205) can includes a stack of dynamic Random Access Memory (DRAM) cores (1210, 1215, 1220, 1225) in a three-dimensional stacked memory architecture (1230). Each of the DRAM cores (1210, 1215, 1220, 1225) can include a plurality of banks (205-1, 205-2, 205-3, 205-4) to store data. The memory (1205) can also include logic layer (1235) which can include an interface (1305) to connect the memory (1205) with a processor (120). The logic layer (1235) can also include a refresh engine (115) that can be used to refresh one of the plurality of banks (205-1, 205-2, 205-3, 205-4) and a Smart Refresh Component (305) that can advise the refresh engine (115) which bank to refresh using an out-of-order per-bank refresh. The Smart Refresh Component (305) can use a logic (415) to identify a farthest bank in the pending transactions in the transaction queue (430) at the time of refresh.

Abstract translation: 公开了一种存储器（1205）。 存储器（1205）可以包括三维堆叠存储器架构（1230）中的动态随机存取存储器（DRAM）核心（1210,1215,1220,1225）堆叠。 每个DRAM内核（1210,1215,1220,1225）可以包括用于存储数据的多个存储体（205-1,205-2,205-3,205-4）。 存储器（1205）还可以包括逻辑层（1235），其可以包括将存储器（1205）与处理器（120）连接的接口（1305）。 逻辑层（1235）还可以包括刷新引擎（115），其可用于刷新多个存储体（205-1,205-2,205-3,205-4）中的一个和一个智能刷新组件（ 305），其可以建议刷新引擎（115）哪个存储体使用无序刷新每次刷新刷新。 在刷新时，智能刷新组件（305）可以使用逻辑（415）来识别事务队列（430）中的待处理事务中的最远存储体。