公开(公告)号：US20240414942A1

公开(公告)日：2024-12-12

申请号：US18808790

申请日：2024-08-19

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： JIEUN LEE ,  MINCHAE KWAK ,  BYUNGSUN KIM ,  ILGOO YOUN ,  SEUNGHAN JO ,  JUNYOUNG JO ,  MINHEE CHOI

IPC: H10K59/121 ,  H01L27/12 ,  H10K59/126 ,  H10K59/131

Abstract: Provided is a display apparatus including: a substrate in which a display element is arranged; a first thin film transistor arranged in the display area and including a first semiconductor layer including silicon and a first control electrode insulated from the first semiconductor layer; a first interlayer insulating layer covering the first control electrode; a second thin film transistor arranged on the first interlayer insulating layer and including a second semiconductor layer including an oxide semiconductor and a second control electrode insulated from the second semiconductor layer; a second interlayer insulating layer covering the second control electrode; a node connection line arranged on the second interlayer insulating layer and connected to the first control electrode via a first contact hole; a first planarization layer covering the node connection line; and a shielding electrode arranged on the first planarization layer to overlap the node connection line.

公开(公告)号：US20240206247A1

公开(公告)日：2024-06-20

申请号：US18592891

申请日：2024-03-01

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： NAYUN KWAK ,  CHULKYU KANG ,  DAESUK KIM ,  ILGOO YOUN ,  DONGSUN LEE ,  SOYOUNG LEE ,  JIEUN LEE ,  JUNYOUNG JO ,  MINHEE CHOI

IPC: H10K59/126 ,  G09G3/3233 ,  H01L27/12 ,  H10K59/124 ,  H10K59/131

CPC classification number: H10K59/126 ,  G09G3/3233 ,  H01L27/1237 ,  H10K59/124 ,  H10K59/131 ,  G09G2300/0426 ,  G09G2300/0819

Abstract: A display device includes a pixel circuit disposed on a substrate, and a display element on the pixel circuit. The pixel circuit includes a first thin-film transistor comprising a first semiconductor layer and a first gate electrode insulated from the first semiconductor layer, a second thin-film transistor comprising a second semiconductor layer and a second gate electrode insulated from the second semiconductor layer, the second semiconductor layer being connected to the first semiconductor layer and the first gate electrode, a first shielding layer overlapping the second semiconductor layer, and a second shielding layer overlapping the second semiconductor layer and stacked on the first shielding layer.

公开(公告)号：US20230172013A1

公开(公告)日：2023-06-01

申请号：US18161434

申请日：2023-01-30

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： NAYUN KWAK ,  CHULKYU KANG ,  DAESUK KIM ,  ILGOO YOUN ,  DONGSUN LEE ,  SOYOUNG LEE ,  JIEUN LEE ,  JUNYOUNG JO ,  MINHEE CHOI

IPC: H10K59/126 ,  H01L27/12 ,  H10K59/124 ,  H10K59/131

CPC classification number: H10K59/126 ,  H01L27/1237 ,  H10K59/124 ,  H10K59/131

Abstract: A display device includes a pixel circuit disposed on a substrate, and a display element on the pixel circuit. The pixel circuit includes a first thin-film transistor comprising a first semiconductor layer and a first gate electrode insulated from the first semiconductor layer, a second thin-film transistor comprising a second semiconductor layer and a second gate electrode insulated from the second semiconductor layer, the second semiconductor layer being connected to the first semiconductor layer and the first gate electrode, a first shielding layer overlapping the second semiconductor layer, and a second shielding layer overlapping the second semiconductor layer and stacked on the first shielding layer.

公开(公告)号：US20210028258A1

公开(公告)日：2021-01-28

申请号：US16938087

申请日：2020-07-24

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： JIEUN LEE ,  Minchae Kwak ,  Byungsun Kim ,  Ilgoo Youn ,  Seunghan Jo ,  Junyoung Jo ,  Minhee Choi

IPC: H01L27/32

Abstract: Provided is a display apparatus including: a substrate in which a display element is arranged; a first thin film transistor arranged in the display area and including a first semiconductor layer including silicon and a first control electrode insulated from the first semiconductor layer; a first interlayer insulating layer covering the first control electrode; a second thin film transistor arranged on the first interlayer insulating layer and including a second semiconductor layer including an oxide semiconductor and a second control electrode insulated from the second semiconductor layer; a second interlayer insulating layer covering the second control electrode; a node connection line arranged on the second interlayer insulating layer and connected to the first control electrode via a first contact hole; a first planarization layer covering the node connection line; and a shielding electrode arranged on the first planarization layer to overlap the node connection line.